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Request of Collaboration

Basic PLL with TSMC 65nm

To design and verify a simple PLL for use as generator of clock signals in System on Chip design. The desired outcome from this project should be the following:

Clock generation for frequencies between 60 MHz and 1.2 GHzInclude PLL-lock signal for system start upLow clock uncertainty below 5% (transition time and jitter)Integer clock divider which can be updated at run timeMinimal area

The resulting IP for these component blocks will be made available to the soclabs community for the upcoming design contest.

Collaborative
Active Project

System Verification of NanoSoC

Performing system-level verification on a System-on-Chip (SoC) design is crucial for ensuring the correct function and overall performance of the entire system, rather than individual components. With NanoSoC, there are multiple options for performing system-level verification.

Collaborative
Case Study
dwf @soton.ac.uk

Building system-optimised AMBA interconnect
Example case-study of using the Arm CMSDK AMBA-AHB Bus-Matrix tools to build system-optimised interconnect.
Collaborative
Active Project

SHA-2 Accelerator Engine

Motivation

At SoC Labs, we have need of an accelerator to test our SoC infrastructure and confirmation of our accelerator wrapper design to get size and performance information as well as to try and get ahead and uncover potential problems researchers may experience trying to put their IP into the reference SoC.

 

Specification

The preliminary design has been broken into two main blocks:

Collaborative
Request of Collaboration

Lightweight DMA Infrastructure
The project aims to produce lightweight SoC Infrastructures using the variety of AMBA bus architectures. An initial NanoSoC infrastructure using AHB for small scale accelerators with low data throughput and complexity is complete. The project is now looking for collaboration on an AXI based SOC, for larger scale accelerators with higher data throughput and added complexity.
Collaborative
Case Study

Efficient Keyword-Spotting on an Arm M7 microcontroller
This 4 month PhD Interdisciplinary Team Project used an Arm M7 to measure actual energy used in different forms of inference and feature extraction for keyword spotting.
Collaborative
Active Project
dflynn-University of Southampton

Arm Cortex-M0 microcontroller
A reference design based on an Arm Cortex-M0 CPU and the Cortex-M0 Design Kit provided in the Corstone-101 subsystem package, available under the Arm Academic Access agreement.
Collaborative
Active Project

Fused: Closed-loop Performance and Energy Simulation of Embedded Systems

Fused is a full-system simulator for modelling energy-driven computers. To accurately model the interplay between energy-availability, power consumption, and execution; Fused models energy and execution in a closed feedback loop.

Collaborative
Active Project
d.wf @ soclabs

Hardware SoC bus level debug agent (v4)
A hardware Finite State Machine on-chip AMBA interconnect controller using a serial ASCII debug protocol, with functional upgrades to Version 4 to support 8-, 16- and 32-bit accesses, to facilitate off-chip validation.
Collaborative
Case Study

3D-stacked cortex-M0 SoC with wireless inter-tier data and power transfer

This project developed a 2-tier 3D-stacked Cortex-M0 SoC, in 65nm CMOS technology, with wireless inter-tier power and data transfer through an inductively coupled bus which achieved 20.3Gbps/mm2 data, and 7.1mW/mm2 power transfer simultaneously through a 250 µm channel. At the time of publishing it was the smallest ever reported inductive data and power link.