
For the first tape out of nanosoc, the instruction memory was implemented using SRAM. Whilst this meant that the read bandwidth from this memory was very fast. It also meant that on a power-on-reset, all the code was erased as SRAM is volatile memory. An alternative use of non-volatile memory would benefit applications where deployment of the ASIC does not allow, or simply time is not available for programming the SRAM after every power up.