Can you please expand on the External I/O interface implementation.

Kind regards,

John.

As Daniel suggests, looking for the sweet spot where the SoC as a system is optimised both in data processing (calculations and their parallelism) and data movement (minimising the time where the bus is not utilised) is aiming to a point where you are able to run the calculations as fast as you can move the data.

As outlined the two aspects to consider;

1)    The SoC integration issue (outside in)
2)    The accelerator design (inside out)

Increasing the data processing capacity can be brute parallelism, just replication of processing blocks or data data specific optimisations, black pixels that are represented as zero which could reduce computation. Does a black pixel in the input image not add any contribution to the distance to all other class members? Holding data is changing less frequently (the unknown example) while you iterate data for say the members of a class?

Increasing utilisation of the system to move the data associated with processing. This is the SoC integration issue. How to maximise the data flowing across the bus into your accelerator. Looking at the asymmetry of data input to calculated outputs.

In this contest pathway, it is not about the ultimate design, it is about your journey in looking at optimisation strategies both in the utility of the SoC infrastructure and the application domain calculations. Perhaps when you have a next view of your design and the thoughts behind it you can share it?

Hi,

We have started work on a new DMA implementation. This will use the DMA35. We are also looking into AXI based implementations for a higher bandwidth SoC reference design. We will add some information shortly.

John.

Hi,

Now as you get into your first SoC design, what in reflection has been a surprise and possibly no well discussed on the course?

john.

In order to move the design beyond an FPGA implementation and towards an ASIC the parts that are dependent on the FPGA fabric will need to be become part of the design so they can be fabricated. We are looking at the AAA IP parts needed for an AXI interconnect design.

Have you decided on the target FPGA environment. We have developed flows for NanoSoC for Xilinx and MPS3 Boards as targets. We would be interested in your choice?

We have published a project on verification of NanoSoC with some details on the Cocotb work but Daniel should be able to provide some additional details.

Daniel,

Thanks for updating the project to split out the NanoSoC AHB implementation from the new AXI implementation. Can you expand a little on the early DMA 350 investigations. 

John.

Hi,

Have you decided on a specific technology node as your physical target?

John.

We have made some changes to Projects and Organisations now that SoC Labs is growing and simple linear display is no longer helpful. We have added geographic visualisation of organisations and separated the Projects into classes such as Reference Designs, Contests and Collaborations.

Now that the Semiconductor Education Alliance is evolving we are getting support from more key industry players and these are joining the community and providing us with some support which we will add more details on soon.

Always happy to hear any improvements people would like.

John.