Daniel has now updated the mixed signal subsystem reference design project, you might want to follow that project as a way to help with your own Architectural Design?

Daniel,

I guess you are working with Philip Leong and Lewis Watts. As you investigate the Technology you may need for the SoC design and the Design Flow stages that will guide you through the milestones stages of taking your design from outline concept to final ASIC you can add them to your profile if they are things you are interested in.

It would be great to see your team developing a Project, either as part of a Competition or just as a general Collaboration.

Look forward to hearing from you?

John.

Hi,

I think it would be helpful if you could add a diagram of the system architecture to the project. That will make it easier for people to understand the system and the the work that is needed. Can you add one?

Architectural Design stage currently has three sub-stages:

1. Specifying a SoC

   Work through the items needed to specify the highest level of design for the SoC.

2. IP Selection

   Pick the IP parts from the Technology section. You might also want to think about your Project Structure and other high level Design Flow considerations.

3. Verification

   You should start to think about how you will validate your SoC design. Creating verification and validation assests as you develop the design is a good working practice.

You should find some helpful examples from some of the other SoC Labs projects.

Happy to help and answer any questions.

Daniel,

Can you add a link here to the code repository? That will make it easier for people.

John.

There is some additional work post tape out in preparation for the testing the die within the test board. Can we capture any learning points here?

Hi,

It would be good to get an update on your milestones at the end of the month.

John.

Hello,

It is nice to welcome an Arm Ambassador on board. I see you have declared interest in the Xilinx FPGA flow. One of our design rationale was to ease the transition from FPGA flows into a full ASIC flow. This does mean instantiating a little more of the SoC in the custom logic as opposed to depending on IP blocks embedded in the fabric. It would be great to know how you would like to get involved in SoC Labs.

John. 

Hi,

How are you getting along with the initial milestone?

John.

Hi,

Hope you are well. There is an interesting project in this years design contest. They are developing some digital signal processing modules for wireless radar sensing.

Interference Detection and Mitigation Accelerator for Automotive Radar SoCs | SoC Labs

I would be keen to build an RF community around SoC Labs.

John.