A physical test environment is required for ASIC devices fabricated following tape out. The nanoSoC test board needs to provide a complete test environment for ASIC designs based on the nanoSoC reference design and enable showcase of any custom designs that utilise it. Reviewing the function of nanoSoC identifies a number of design criteria for the test board:
Serial Wire Debug (SWD) and UART debugger interfaceGPIO driver interface including data transportPower supply and monitoringClock and reset controlBased on these requirements, the following test board is under development:
The integration of the DMA350 into the nanosoc re-usable SoC architecture will improve the transfer bandwidth on DMA channels within the SoC. This project integrates the DMA 350 into nanosoc, validates the integration and functionality of the DMA 350, and compares the performance of the DMA 350 to the PL230, that was the initial DMA controller integrated into nanosoc.
Daniel Newbrook
David Flynn