The Arm Cortex-M55 AIoT SoC design platform is an AIoT subsystem that allows custom SoC designers to integrate their hardware circuits and embedded software for differentiation. The platform is developed by TSRI (Taiwan Semiconductor Research Institute) to support academic research on SoC design. It's built on the Arm Corstone-300 reference package, featuring the Cortex-M55 CPU and Ethos-U55 NPU.

On-chip SRAM in ASICs can use a significant area, which equates to a significant cost. One solution is to make the memory off-chip. This project explores the use of Arm IP to create an SRAM chiplet design. The benefit  is that standard memory chiplets can be fabricated at lower cost and used across multiple projects, miminising silicon area to the unique project needs.

The aim of this project is to define a mixed signal subsystem for the nanosoc reference design. 

The mixed signal subsystem should be able to sample analog signals at a regular sampling rate, and transmit a digital representation of this signal to the rest of the nanosoc system. In order to interface with real-world signals in a digital System on Chip ("SoC"), an analog to digital conversion ("ADC") is needed. 

A physical test environment is required for ASIC devices fabricated following tape out. The nanoSoC test board provides a complete test environment for ASIC designs based on the nanoSoC reference design and enables the showcase of any custom designs that utilise it.  Reviewing the function of nanoSoC identifies a number of design criteria for the test board:

The integration of the DMA350 into the nanosoc re-usable SoC architecture will improve the transfer bandwidth on DMA channels within the SoC.  This project integrates the DMA 350 into nanosoc, validates the integration and functionality of the DMA 350, and compares the performance of the DMA 350 to the PL230, that was the initial DMA controller integrated into nanosoc.