Competition 2024
Competition: Hardware Implementation

Monitoring and enhancing plant growth in space ecosystems

This project focuses on developing a plant growth monitoring system for space exploration missions using the ARM Cortex-M0 microcontroller core. The projects aim to develop a SOC based on ARM M0 core for interactive plant monitoring by interfacing AHB lite, GPIO, timers, and communication protocols such as UART, I2C, SPI, and co-processors.  This project also proposes two co-processors for interactive plant monitoring and control. One AI co-processor for classification and prediction of plant and environmental data. Another coprocessor acts as a sensor gateway to control the data from various sensors. The system aims to provide real-time data on environmental parameters crucial for plant growth, especially in space, enabling users to monitor and optimize the conditions for their plants' health and productivity. The objective is to create an efficient solution to monitor and optimize plant growth in the unique environment of space. The system integrates sensors for measuring temperature, humidity, light intensity, CO2 levels, and nutrient availability, specifically designed for space applications, with the ARM Cortex-M0 core. Firmware is developed using the embedded C programming language to interface with the sensors, collect real-time data, and process it for plant health and growth monitoring. A user-friendly interface makes the visualization of plant growth data and environmental factors possible. The ARM Cortex-M0 core enables remote control of environmental variables, including temperature and humidity, optimizing plant growth based on real-time data.  The project also emphasizes power optimization, maximizing operating duration on constrained power resources in space by utilizing low-power modes of the ARM Cortex-M0 processor. The anticipated results include a fully functional system for tracking plant growth, real-time environmental parameter monitoring, remote control capabilities, and adequate power management. Research, sensor integration, firmware development, user interface design, remote monitoring and control implementation, power optimization, documentation, and project completion are all covered in the twelve-week project timetable.    This project's successful completion will advance knowledge of how plants grow in microgravity and aid efforts to colonize space in the future. It will also increase the viability of long-duration space trips.

 

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Team

Name
Aswani AR
Research Area
AI Chip design
Role
Research Scholar

Comments

Hi,

As we are now into the start of October it would be good to get an update on your milestones at the end of September.

We need to understand if it is likely you will be making progress so we can progress a tape out.

If you need any help or support for the project please let us know.

We look forward to hearing from you.
 

It was good to meet you on the video collaboration call today. As we discussed on the call it would good in the coming week to:

  • look at the project from Sydney and what they have shared so far. They have a good split of work between the sensor subsystem and the digital SoC. Expanding the description of your "sensor gateway to control the data from various sensors" in a similar way will help. 
  • confirm details of the project development environment and design flows. You mentioned the use of Socrates as an overall SoC architecture design tool. It may be helpful to look at some existing SoC designs, such as nanoSoC as well as David's project on design AMBA interconnect. Our hope is that the nanoSoC reference design should be easy to adopt for your application. Sydney have used Verilator for part of their environment. There is the description of how to use the Xilinx FPGA environment in the example design flows. There are other choices and we are happy to help look at what you have available and need. Can you also confirm you have AAA access to all the IP parts you need? 
  • Determine the sampling rates, so for the "real-time data on environmental parameters crucial for plant growth" what is the frequency of variation in these environmental parameters and how much data are we going to flow through the SoC. This is also going to determine the latency demands for the "AI co-processor for classification and prediction". 
  • In terms of the software environment you state "Firmware is developed using the embedded C programming" which is the same as the bare metal implementation on nanoSoC. It would be good to list the parts of the sensor gateway that need control and the necessary list of driver functions that will be needed. 

If we have a clearer view of these things then the project will hopefully move forward more quickly.

We look forward to hearing from you.

It would be good to see you plan out your initial milestones. You can follow some of the generic design flow stages or define your own.

The generic flow Architectural Design stage currently has three sub-stages:

  1. Specifying a SoC

    Work through the items needed to specify the highest level of design for the SoC. Daniel above asks some for a block diagram which always helps convey your design.

  2. IP Selection

    Pick the IP parts from the Technology section. You have listed the main M0 processor IP. What IP will you adopt for other functions, eg. will you use the PL011 UART IP block and will you adopt the APB bus? You might also want to think about your Project Structure and other high level Design Flow considerations.

  3. Verification

    You should start to think about how you will validate your SoC design. Creating verification and validation assests as you develop the design is a good working practice.

You should find some helpful examples from some of the other SoC Labs projects.

Happy to help and answer any questions.

Hi,

We've just updated the nanosoc accelerator project repository, there is now a new way to configure nanosoc including how to include the ADC's.

If you go into the nanosoc_tech directory there is a file nanosoc.config. If you add text after any of the ADC_x_INCLUDE =  then the APB bus will be configured for an ADC, and the verilog-ams model of the ADC will be included (this is not synthesizable for FPGA or ASIC - we're working on making this available soon). There is also a test for the adc subsystem called adc_tests. This can be run from the nanosoc_tech directory with 

make run_vcs TESTNAME=adc_tests

Unfortunately at the moment, synopsys VCS is the only supported simulator for the ADC, but we are working on this

Daniel

The 2023/24 version of the nanoSoC reference design has been used to tape the following projects with custom accelerators and will hopefully give you some help in developing your own project.

The die from the ASIC fabrication are back from manufacture and are being tested using the nanoSoC test board. 

If you need any help with your project please let us know.

John.

Hi, Good to see you have resubmited this for the current contest.
Is the sensor frontend going to be an analog subsystem in the SoC or are you planning to use external components for this?
It could be good to get a sense of your design if you could add a block diagram of what you are planning to implement including which components are part of the SoC and what are external interfaces

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Project Creator
Alex James

Dean at Kerala University of Digital Sciences, Innovation and Technology
Research area: Neural network, Mixed signal circuits

Technology

Cortex-M0 Cortex-M0

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