Cortex-A53

The Cortex-A53 processor has an 8-stage, symmetric dual-issue in-order pipeline implementing the 64-bit Armv8-A architecture with one to four cores with automatic data cache coherency, the shared Level 2 cache can be up to 2MB, 128 bit ACE or CHI coherent system bus interface.
The A53 pipeline supports symmetric dual-issue of most instructions, compared to the A7 which can only handle integer instructions in the second slot.
Explore This Technology
Contribution
Projects Using This Technology
Competition
Competition: Hardware Implementation

Competition
Competition: Hardware Implementation

Known Good Die
Experts and Interested People
Members
Research Area
Multiprocessor SoC (MPSoC) design, Neural network learning algorithm design, Reliable system design, VLSI/CAD design, Smart manufacturing
Role
Associate Professor
Actions
Add new comment
To post a comment on this article, please log in to your account. New users can create an account.