Cortex-M23

The Cortex-M23 implements the ARMv8-M architecture with a two-stage in-order pipeline supporting Thumb-1 and subset of Thumb-2 instructions with hardware multiply and divide in a low gate count similar to M0 and aimed at energy efficient embedded applications.

The Nested Vector Interrupt Controller (NVIC) supports up to 240 interrupt inputs from peripherals with 4 priority levels supporting deterministic and fixed-latency interrupt handling.

TrustZone support for a Secure and a Non-secure state

The Memory Protection Unit supports the PMSAv8 Protected Memory System Architecture model with up to 16 regions.

The bus mechanism is AMBA 5 AHB with optional single cycle I/O.