Corstone Subsystems

Corstone Subsystems combines the various system IP components for a specific processor and Arm architecture to simplify System on Chip designs. The contain reference designs that utilise the IP blocks to reduce design and verification effort.

Projects Using This Technology

Competition 2023
Competition: Hardware Implementation

Real-Time Edge AI SoC: High-Speed Low Complexity Reconfigurable-Scalable Architecture for Deep Neural Networks

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Research Area
Neural Networks Acceleration
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Research Assistant
 
Research Area
Neuromorphic Chip Designing, VLSI architecture designing, AI/ML
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Research Scholar
 
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Research Area
Neuromorphic IC Design & Hardware Acceleration of Deep Learning
Role
Research Scholar
 
Research Area
SoC Design
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Lecturer

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Comments

Along with a brief description for each corestone subsystem on this page, we should also document the IP used in each subsystem and link it back to the relevant page in technology. 

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