Corstone Subsystems

Corstone Subsystems combines the various system IP components for a specific processor and Arm architecture to simplify System on Chip designs. The contain reference designs that utilise the IP blocks to reduce design and verification effort.

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Tarun Gupta
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Neural Networks Acceleration
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Research Assistant
 
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Anagha Nimbekar
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Neuromorphic Chip Designing, VLSI architecture designing, AI/ML
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Dinesh
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Neuromorphic IC Design & Hardware Acceleration of Deep Learning
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Comments

Along with a brief description for each corestone subsystem on this page, we should also document the IP used in each subsystem and link it back to the relevant page in technology. 

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