Cortex-M3
The Cortex-M3 implements the ARMv7-M architecture supporting Thumb-1 and Thumb-2 instructions with a 3-stage in-order pipeline, with hardware Divide and Multiply, and an additional nonprivileged mode (User Thread). It supports Bit-banding in the lowest 1MB of the SRAM and Peripheral memory allowing individual bits to be toggled without performing a read-modify-write.
The Nested Vector Interrupt Controller (NVIC) supports up to 240 interrupt inputs from peripherals with programmable priority levels from 8 to 256 levels.
The bus mechanism implements the 3x AHB-lite protocol interfaces.
Optional Instruction (Embedded Trace Macrocell), Data Trace (DWT), and Instrumentation Trace (ITM), JTAG and Serial Wire Debug ports. Up to 8 breakpoints and 4 watchpoints.
Explore This Technology
![Diagram of M3 processor](/sites/default/files/styles/large/public/2021-09/Cortex-M3.png?itok=90xvyHzX)
Projects Using This Technology
![](/sites/default/files/2024-03/Mixed%20signal%20controller2.png)
![](/sites/default/files/2023-06/RMC_SoC.png)
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