CoreSight SoC-400 is a debug subsystem design with Arm IP blocks for debug and trace in support of multi-processor SoCs. It contains components to implement CoreSight functionality for debug, trace, cross-triggering and timestamps. 

The debug subsystem components for access and control of the system, sources that generate trace data,  links that flow of trace data through the system, sinks that collect trace data and timestamps for the system. 

access and control is via the Debug Access Port and the Embedded Cross Trigger supporting multiple SoC subsystems.

link components include, the AMBA Trace Bus (ATB) to transfers trace data through the system, Funnel which merges multiple ATB buses, and Replicator supports the connection of two trace sinks.

sources (ATB masters) include the Program Trace Macrocell,  and under separate license, System Trace Macrocell, Trace Memory Controller and Embedded Trace Macrocell.

sinks (ATB slaves) include Trace Port Interface Unit for off chip transfer and Embedded Trace Buffer (ETB) for on-chip storage of trace data.

timestamp components include generator, encoder and decoder.

Explore This Technology

Diagram of CoreSight SoC-400 components in a SoC
Copyright © 1995-2021 Arm Limited (or its affiliates). All rights reserved.

Projects Using This Technology

Experts and Interested People


Research Area
soc design verification
design verification


Interested in this topic? Log-in to Add to Your Profile

Add new comment

To post a comment on this article, please log in to your account. New users can create an account.