Cortex-R Series

The Cortex-R Series is aimed at embedded Systems for precisely defined applications with either deterministic real time performance or  safety critical demands. The series of processors conforms to a specific Arm architecture profile for the class of processors, the ARMv8-R AArch32 which supports virtualization via a hypervisor and  ARMv7-R which supports a single real time operating system. 

These profiles define a simple approach to memory protection for safe operation that also benefits the low latency demand for real time response, that is to have a direct mapping between the virtual address and the 32-bit physical address of the memory system. In addition memory is protected in hardware using registers to define protection regions of memory making memory checking deterministic. It is a a unified memory protection scheme and does not support regions for instruction and data using attributes including access permissions. These can be used by the operating system to ensure only allowed processes access memory locations.  The main difference in memory protection between the ARMv7-R and ARMv8-R profiles is in how memory region size is handled. 

In ARMv7-R memory regions are defined as a power of two in size, where a given region has to be aligned to a base address equal to an integer multiple of its size, this provides a low logic gate count implementation. In ARMv8-R memory regions can start and end at any address equal to an integer multiple of 64 bytes and has more efficient register access.

Armv8-R re-implements the Data Memory Barrier  (DMB) instruction for a memory barrier that ensures the ordering of observations of memory accesses and the Data Synchronization Barrier (DSB) instruction memory barrier that ensures the completion of memory accesses. It also implements a new instruction, Data Full Barrier (DFB) which is an alias of DSB completion memory barrier but orders memory accesses irrespective of their Exception level.

Armv8-R permits a floating-point implementation that supports only single-precision floating-point instructions using t only floating-point registers D0-D15.



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