CoreLink CCI-550

CCI-550 Cache Coherent Interconnect block diagram
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CCI-550 provides high bandwidth access between CPUs and other SoC blocks including shared main memory supporting Arm big.LITTLE processing techniques with up to seven ACE/ACE-Lite masters ACE (max 6) for Arm processors, ACE-Lite (max 6) Mali GPU, etc. and seven AXI4 slaves for memory (max 6), system peripherals, etc.

It implements a snoop filter within the interconnect that maintains a directory of all cache contents which avoids broadcasting coherency messaging to all agents improving latency and power consumption over the CCI-400. 

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