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In partnership with Canada
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Geographical support for Canada

This collaboration project is aimed at providing specific tailored activities to the local geography in Canada by developing local actions that will help stimulate academics and their institutions and the broader semiconductor industry supporters to create new and exciting SoC design projects. 

It may include holding specific local physical meetups where people can exchange design ideas.

It may include utilising locally provided routes to fabrication.

It may include sharing hard to locate test capability across academic institutions.

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Active Project

System Verification of NanoSoC

Performing system-level verification on a System-on-Chip (SoC) design is crucial for ensuring the correct function and overall performance of the entire system, rather than individual components. This project is aimed at developing the necessary resources and design flow stages for the verification of the NanoSoC reference design.

Architectural Design: Verification Methodology

With NanoSoC, there are multiple options for performing system-level verification. 

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Active Project

SHA-2 Accelerator Engine

Motivation

At SoC Labs, we have need of an accelerator to test our SoC infrastructure and confirmation of our accelerator wrapper design to get size and performance information as well as to try and get ahead and uncover potential problems researchers may experience trying to put their IP into the reference SoC.

 

Specification

The preliminary design has been broken into two main blocks:

Collaborative
Active Project
dflynn-University of Southampton

Arm Cortex-M0 microcontroller
A reference design based on an Arm Cortex-M0 CPU and the Cortex-M0 Design Kit provided in the Corstone-101 subsystem package, available under the Arm Academic Access agreement.
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Fused: Closed-loop Performance and Energy Simulation of Embedded Systems

Fused is a full-system simulator for modelling energy-driven computers. To accurately model the interplay between energy-availability, power consumption, and execution; Fused models energy and execution in a closed feedback loop.

Collaborative
Active Project
d.wf @ soclabs

Hardware SoC bus level debug agent (v4)
A hardware Finite State Machine on-chip AMBA interconnect controller using a serial ASCII debug protocol, with functional upgrades to Version 4 to support 8-, 16- and 32-bit accesses, to facilitate off-chip validation.