SoC Labs and Arm have announced a joint 'Bridging the Skills Gap' SoC Design Contest that will run during 2023. This example design flow is provided to help groups engage with the contest. It is not prescriptive but tries to provide useful information in creating a design flow environment in which to develop your SoC design. The information covers example design flow elements that can be used as a basis for your design flow for taking part in the competition. You are free to use a design flow of your own if you have already established methods. More details are provided below or you can take a look at the Getting Started information.
There are two separate tracks within the SoC Design Contest, aimed at the research innovation and talent development issues respectively:
HW Implementation / research innovation:
FPGA design flow: Research groups interested in the contest can submit a project, either one of their own designs or using some of the community developed or Arm base reference designs being made available. The design could be new or from an already in-flight research project. The NanoSoc reference SoC design has been provided to help people who are developing custom hardware acceleration for new forms of compute. If you are new to FPGA design we have made available the Cortex-M0 reference design which could be a starting point of a simple SoC design. An example Xilinx FPGA design flow has also been provided to help. Groups who have experience of FPGA development or design underway may well have an existing or preferred design environment and flow.
ASIC design flow: Research groups interested in taping-out their designs may share details of their proposed ASIC design and flow to have an opportunity to join a free Arm and partner-sponsored shuttle later in 2023. The target process technology for this shuttle is expected to be 65nm but groups can use other flows and technology nodes if they have a tape out route. One of the design principles adopted for the SoC Labs reference designs is to provide a quick and simplified route to FPGA development to ASIC tape out and verification of SoC systems. The NanoSoc reference SoC design provides some alternative blocks than those embedded in the Xilinx Vivado fabric that simplify development for a Xilinx Zynq FPGA board but would be absent in an ASIC flow. Using these blocks in a design allows the design to be developed in an FPGA environment but are also fabricated in the ASIC.
Collaboration/Education: In this track the focus is on developing skills and collaborations as opposed to the hardware design itself.
Groups may wish to use the NanoSoc reference SoC design IP and the example of integrating custom accelerator logic. It is not important if you do not have a unique accelerator design. The important aspect is your journey and the project can be an effective re-use of an existing accelerator logic or commonly used algorithm. Another example might be a group that has implemented an FPGA implementation but to date has not undertaken an ASIC tape out. The learning and the project in this case is about translating the work to an ASIC flow.
Groups or individuals quite new to SoC design might look to the Cortex-M0 reference design to create a basic SoC. Academics involved in teaching SoC design may submit a project summary detailing their approach improving SoC design activities. An example might be creating support for students projects that help build real world System on Chip (SoC) design and development skills. This might be supported by a virtual SoC development environment and using virtualised FPGA development boards.
If you have any suggestions or other points that may help the community please add a comment below.