Timing closure

Timing closure completes the process of adjusting all the design elements and the signal paths between them to meet the overall system timing requirements.

It involved analysis of all path delays between elements and the intrinsic delays of element operation within the synchronizing clock pulses and modifying the physical design to remove the timing failures caused by propagation delays longer than the clock cycle time.

Closure of a physical design is meet when all timing requirements are satisfied.

Projects Using This Design Flow

Related Project Milestones

Project Name Target Date Completed Date Description
Fast-kNN: A hardware implementation of a k-Nearest-Neighbours classifier for accelerated inference Timing closure
SRAM Chiplet Timing closure

Aim to close design at 1GHz

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