Trace Memory Controller

Image of CoreSight Trace Memory Controller
Copyright © 1995-2021 Arm Limited (or its affiliates). All rights reserved.

The Trace Memory Controller (TMC) enables trace data to be passed to system memory and other high speed devices and links in the System-on-Chip as part of the debug system. Debug system designs include the following components:

Embedded Trace Buffer (ETB) enables trace data to be stored in a dedicated SRAM, used as a Circular Buffer.

Embedded Trace FIFO (ETF) enabled trace data to be stored used either as a Circular Buffer or as a FIFO.

Embedded Trace Router (ETR) enables trace data to be routed over an AXI bus to system memory or other AXI slaves.


Explore This Technology

Projects Using This Technology


Log-in to Add to Your Profile

Add new comment

To post a comment on this article, please log in to your account. New users can create an account.