There has been much request within the SoC Labs community for an Arm A-Class SoC that can support a full operating system platform, undertake more complex compute tasks and enable more complicated software loads. The Cortex-A53 is Arm's most widely deployed 64-bit Armv8-A processor and can provide these capabilities with power efficiency

This project aims to design and implement a high capacity memory subsystem for Arm A series processor based SoC designs.  The current focus of the project is the design and implementation of a Memory Controller for DDR4 memory. 

The Synopsys HAPS® System adds additional capabilities to the FPGA-based prototyping environments SoC Labs can use to support projects. The HAPS® system provides a greater amount of logic resources supporting development of larger SoC designs. It can be used to support multiple projects simultaneously. It is used by many semiconductor companies, including arm for their CPU verification. This collaboration project will use the HAPS® system in SoC Labs projects and share with the community experience in utilising such systems.

The Arm PL022 provides an interface for synchronous serial communication with peripheral devices connected to the  SoC via the Advanced Peripheral Bus (APB). It supports a choice of interface operation, Motorola compatible Serial Peripheral Interface (SPI), National Semiconductor Microwire, or Texas Instruments synchronous serial interface. See the Techology page for details. 

To design and verify a simple PLL for use as generator of clock signals in System on Chip design. The desired outcome from this project should be the following:

The resulting IP for these component blocks will be made available to the soclabs community for the upcoming design contest.

The aim of the project will be to establish the tool chain and flows to demonstrate Event-B refinement to a Register Transfer Level implementation that can target an FPGA implementation. Previous European, EC Information and Communication Technologies FP7 DEPLOY and European Union ICT Project ADVANCE developed VHDL code generation from Event-B models. A number of projects within these and other research programmes have looked at the required process flows. The Rodin Platform is an open source Eclipse-based IDE for Event-B.