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A53 simplified testbench
SoClabs

Arm Cortex-A53 processor

There has been much request within the SoC Labs community for an Arm A-Class SoC that can support a full operating system platform, undertake more complex compute tasks and enable more complicated software loads. The Cortex-A53 is Arm's most widely deployed 64-bit Armv8-A processor and can provide these capabilities with power efficiency

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High Capacity Memory Subsystem Development
Introduction

This project aims to design and implement a high capacity memory subsystem for A series CPU based SoCs. 

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Use of the Synopsys HAPS® FPGA-based prototyping environment

The Synopsys HAPS® System adds additional capabilities to the FPGA-based prototyping environments SoC Labs can use to support projects. The HAPS® system provides a greater amount of logic resources supporting development of larger SoC designs. It can be used to support multiple projects simultaneously. It is used by many semiconductor companies, including arm for their CPU verification. This collaboration project will use the HAPS® system in SoC Labs projects and share with the community experience in utilising such systems.

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Interfacing with the Arm PL022 within a cocotb testbench

The Arm PL022 provides an interface for synchronous serial communication with peripheral devices connected to the  SoC via the Advanced Peripheral Bus (APB). It supports a choice of interface operation, Motorola compatible Serial Peripheral Interface (SPI), National Semiconductor Microwire, or Texas Instruments synchronous serial interface. See the Techology page for details. 

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Basic PLL with TSMC 65nm

To design and verify a simple PLL for use as generator of clock signals in System on Chip design. The desired outcome from this project should be the following:

Clock generation for frequencies between 60 MHz and 1.2 GHzInclude PLL-lock signal for system start upLow clock uncertainty below 5% (transition time and jitter)Integer clock divider which can be updated at run timeMinimal area

The resulting IP for these component blocks will be made available to the soclabs community for the upcoming design contest.

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DMA Infrastructure Developments
The aim of of this project is to produce a variety of DMA Infrastructures for reusable SoC reference designs containing Arm-based microprocessors that can be picked up and used by researchers, academics and students with minimal modifications to allow them to easily implement experimental systems.
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Event-B to FPGA process flows

The aim of the project will be to establish the tool chain and flows to demonstrate Event-B refinement to a Register Transfer Level implementation that can target an FPGA implementation. Previous European, EC Information and Communication Technologies FP7 DEPLOY and European Union ICT Project ADVANCE developed VHDL code generation from Event-B models. A number of projects within these and other research programmes have looked at the required process flows. The Rodin Platform is an open source Eclipse-based IDE for Event-B.