The Arm PL022 provides an interface for synchronous serial communication with peripheral devices connected to the  SoC via the Advanced Peripheral Bus (APB). It supports a choice of interface operation, Motorola compatible Serial Peripheral Interface (SPI), National Semiconductor Microwire, or Texas Instruments synchronous serial interface. See the Techology page for details. 

To design and verify a simple PLL for use as generator of clock signals in System on Chip design. The desired outcome from this project should be the following:

The resulting IP for these component blocks will be made available to the soclabs community for the upcoming design contest.

The aim of the project will be to establish the tool chain and flows to demonstrate Event-B refinement to a Register Transfer Level implementation that can target an FPGA implementation. Previous European, EC Information and Communication Technologies FP7 DEPLOY and European Union ICT Project ADVANCE developed VHDL code generation from Event-B models. A number of projects within these and other research programmes have looked at the required process flows. The Rodin Platform is an open source Eclipse-based IDE for Event-B.