This section on design flows contains  example flows with information on specific flow/tool implementations. Tool vendors have made different choices on how to implement specific steps in the four high level generic design flow stages with variations in file forms and even subtle differences in how language constructs are implemented. This means that a design that will pass verification in one tool chain may not pass verification in another tool chain. Additionally their are significant variations in warning messages across tool chains.  

The example flows should describe the design flow steps that takes a System on Chip design from initial concept to final implementation with descriptions on how the specific flow implementation delivers the requirement of the general flow steps. 

An early ‘example flow’ was developed to describe the Xilinx(R) PYNQ(R) platform to allow early hardware/software co-design prior to moving to a full ASIC design flow. This area should develop as the community adds additional example flows that allow us to share and discuss how these flow deliver the requirement of the general design flow steps. 

Each 'example flow' should instantiate the steps of the generic flow with specific information, this is similar to an object oriented model of a 'base class' in the generic flow being used to instantiate a specific class in the 'example flow'.

The open source community, Arm and other 3rd party are all looking to provide design support environments that simplify the SoC design task, this part of the site is an area for material and discussions on such tool chains and example design flows.

Example design flows have been added that have been used on projects and we encourage the community to share more examples.