Spiking Neural Networks (SNNs) require processing a large number of spikes to achieve high classification accuracy. However, this results in frequent memory accesses to fetch synaptic weights, which significantly increases energy dissipation in SNN systems. To address this challenge, we propose a unique technique called the Repetitive Spike Train (RST) method. By exploiting the temporal similarity of spike trains across time steps, RST minimizes redundant spike train updates and reduces memory read/write operations.

Aspen is a unified accelerator for deep neural network (DNN)-based extended reality perception workloads. Aspen proposes a mixed-precision quantization scheme using the posit datatype to reduce memory usage while maintaining accuracy, a DNN accelerator for mixed-precision posit datatypes, and efficient data prefetching and data layout to minimize data reorganization. The Aspen system-on-chip has an Arm Cortex-M3 CPU, a mixed-precision posit-based DNN accelerator, and 4 megabytes of SRAM partitioned into eight 512 KB banks, connected through a 128-bit-wide interconnect.

This program is dedicated to the development of a System on Chip (SoC) platform, specifically designed to support learning and research activities within Indonesian academic institutions. The platform serves as an educational and research tool for students, lecturers, and researchers to gain hands-on experience in digital chip design.

The instruction memory in the first tape out of nanosoc was implemented using SRAM. The benefit was the read bandwidth from this memory was very fast, the downside was on a power-on-reset, all the code was erased as SRAM is volatile memory. An alternative use of non-volatile memory would benefit applications where  deployment of the ASIC does not allow, or simply time is not available for programming the SRAM after every power up. 

The Arm Cortex-M55 AIoT SoC design platform is an AIoT subsystem that allows custom SoC designers to integrate their hardware circuits and embedded software for differentiation. The platform is developed by TSRI (Taiwan Semiconductor Research Institute) to support academic research on SoC design. It's built on the Arm Corstone-300 reference package, featuring the Cortex-M55 CPU and Ethos-U55 NPU.

As part of plans for continued development of nanoSoC one area that requires improvement is the power structure of system. The first iteration of nanoSoC contained 2 power domains: the accelerator domain and the remainder of the SoC. Both power domains were connected to external pins to allow connection to separate external voltage regulators and power measurement ICs, as implemented in the first version of the nanoSoC testboard.

There is growing interest within the SoC Labs community for an Arm A-Class SoC that can support a full operating system, undertake more complex compute tasks and enable more complicated software directed research. The Cortex-A53 is Arm's most widely deployed 64-bit Armv8-A processor and can provide these capabilities with power efficiency. 

This project aims to design and implement a high capacity memory subsystem for Arm A series processor based SoC designs.  The current focus of the project is the design and implementation of a Memory Controller for DDR4 memory. 

The Synopsys HAPS® System adds additional capabilities to the FPGA-based prototyping environments SoC Labs can use to support projects. The HAPS® system provides a greater amount of logic resources supporting development of larger SoC designs. It can be used to support multiple projects simultaneously. It is used by many semiconductor companies, including arm for their CPU verification. This collaboration project will use the HAPS® system in SoC Labs projects and share with the community experience in utilising such systems.