All Projects

You can use the filters below to restrict this based on Technology or Skills.
Competition 2024
Competition: Hardware Implementation
Own created Image

Interference Detection and Mitigation Accelerator for Automotive Radar SoCs

Advancements in electronics, wireless communications, and sensing technologies have made possible a multitude of smart sensing features in automotives. Integrating high-frequency sensors, digital signal processors and hardware accelerator engines on a single system on a chip (SoC) enhances sensing computation potential of radar sensors utilized in automotives.

Reference Design
Active Project
3D Render of nanoSoC test board

nanoSoC Test/development Board

A physical test environment is required for ASIC devices fabricated following tape out. The nanoSoC test board needs to provide a complete test environment for ASIC designs based on the nanoSoC reference design and enable showcase of any custom designs that utilise it. Reviewing the function of nanoSoC identifies a number of design criteria for the test board:

Serial Wire Debug (SWD) and UART debugger interfaceGPIO driver interface including data transportPower supply and monitoringClock and reset control

Based on these requirements, the following test board is under development:

Competition 2024
Competition: Hardware Implementation

Arrhythmia Analysis Accelerator : A-Cube

We propose the A-Cube design methodology to create medical decision support on the edge. The design and implementation of an atrial fibrillation detector hardware core was selected as a proof-of-concept study. To facilitate the required atrial fibrillation functionality, we adopted an established AI model, based on Long Short-Term Memory (LSTM) technology for hardware implementation. The adaptation was done by varying design parameters such as data window and the number of LSTM units.

Competition 2024
Competition: Hardware Implementation

Battery Management System-on-chip (BMSoC) for large scale battery energy storage

Battery storage systems are an important source for powering emerging clean energy applications. The Battery Management System (BMS) is a critical component of modern battery storage, essential for efficient system monitoring, reducing run-time failures, prolonging charge-discharge lifecycle, and preventing battery stress or catastrophic situations. The BMS performs functionalities such as data acquisition and monitoring, battery state estimation, cell equalization, and charge protection, making it computationally intensive to manage large scale battery storage.

Collaborative
Request of Collaboration

Basic PLL with TSMC 65nm

To design and verify a simple PLL for use as generator of clock signals in System on Chip design. The desired outcome from this project should be the following:

Clock generation for frequencies between 60 MHz and 1.2 GHzInclude PLL-lock signal for system start upLow clock uncertainty below 5% (transition time and jitter)Integer clock divider which can be updated at run timeMinimal area

The resulting IP for these component blocks will be made available to the soclabs community for the upcoming design contest.

Competition 2024
Competition: Collaboration/Education

A digital audio dynamic range compression accelerator for mixed-signal SoC
Compression Overview

The dynamic range processor is a DSP function which does as it says on the tin; it compresses the dynamic range of the incoming signal. This is used most commonly in the music industry for its effects on the perceived loudness of audio. It is also used extensively in hearing aids to compensate for the user’s reduced dynamic range of hearing. In this project a hardware accelerator is developed for the purpose of dynamic range compression of digital audio. This accelerator will be implemented in a mixed-signal infrastructure.

Reference Design
Active Project

DMA 350 integration with nanoSoC

The integration of the DMA350 into the nanosoc re-usable SoC architecture will improve the transfer bandwidth on DMA channels within the SoC.  This project integrates the DMA 350 into nanosoc, validates the integration and functionality of the DMA 350, and compares the performance of the DMA 350 to the PL230, that was the initial DMA controller integrated into nanosoc.

Competition 2023
Competition: Collaboration/Education

Wireless smart machine box for industrial IoT fault detection and notification
Frequent collisions and vibrations mean machinery components in modern factories suffer from wear and aging. Bearings and gears play a significant role. This work developed a wireless smart machine box for industrial IoT fault detection and notification. The Arm based SoC design performs feature extraction from the sensed vibration data and AXI based Direct Memory Access (DMA) to support local Random Forest machine learning. Data is also transmitted via a wireless sensor network to cloud based actions.
Competition 2023
Competition: Hardware Implementation

A 28nm Motion-Control SoC with ARM Cortex-M3 MCU for Autonomous Mobile Robots

Autonomous mobile robots (AMRs) have been proven useful for smart factories and have the potential to revolutionize critical missions, such as disaster rescue. AMRs can perceive the environment, plan for assigned tasks, and act on the plan. Motion control is critical to the robot's action, which is accomplished through trajectory optimization to refine the robot's states using a physics model. However, the high computational complexity of trajectory optimization poses significant challenges for AMRs with limited power and computing resources.

Collaborative
Active Project

System Verification of NanoSoC

Performing system-level verification on a System-on-Chip (SoC) design is crucial for ensuring the correct function and overall performance of the entire system, rather than individual components. With NanoSoC, there are multiple options for performing system-level verification.