All Projects

You can use the filters below to restrict this based on Technology or Skills.
Competition 2025
Competition: Hardware Implementation

ASIC for parallel channel tuning on Reconfigurable Intelligent Surfaces

Reconfigurable Intelligent Surfaces (RIS) are planar structures composed of large arrays of tunable elements that can dynamically redirect, reflect, or shape wireless signals in the environment.

Reference Design
Active Project
PCK600 to SIE300 subsytem
dwn @ soclabs

PCK600 Integration in megaSoC

The PCK600 Arm IP provides components to allow a power control infrastructure to be distributed in a SoC in order to make a design energy efficient. Arm provide the IP as part of their Power Control System Architecture that can be used to control the power states of various parts of the system. This control of the power infrastructure is achieved through the use of the Power Policy Unit (PPU). This unit has an APB interface to allow for software control, and some low power interfaces that can connect to the power controllable IP within the system.

Competition 2025
Competition: Collaboration/Education

RF-Powered Sensor Platform for Intelligent Groceries Transportation Monitoring

This project aims to develop an advanced RF energy harvesting (EH) receiver chip specifically designed to power embedded sensors for monitoring the condition of groceries during transportation. The receiver chip captures wireless energy transmitted from phased array antennas and converts it into electrical power that is used to operate onboard sensors, which continuously monitor critical parameters such as temperature and humidity inside delivery trucks.

Competition 2025
Competition: Hardware Implementation

Neural Activity Processor

Stroke and epilepsy are among the most common debilitating neurological conditions, with a worldwide prevalence of 100 million people (World Stroke Organization, 2022) and 50 million people (World Health Organization, 2024), respectively. Present-day approaches for treating neurological and neurosurgical conditions include physiotherapy, pharmacological treatment, surgical excision, and interventions such as deep brain stimulation.

Competition 2025
Competition: Collaboration/Education
An Efficient Hardware-based Spike Train Repetition for Energy-constrained Spiking Neural Networks

In the context of Industry 4.0, handwritten digit recognition plays a vital role in numerous applications such as smart banking systems and postal code detection. One of the most effective approaches to tackle this problem is through the use of machine learning and neural network models, which have demonstrated impressive accuracy and adaptability in visual pattern recognition tasks.

Competition 2025
Competition: Hardware Implementation
Aspen annotated die photo

Aspen: A 630 FPS Real-Time Posit-Based Unified Accelerator for Extended Reality Perception Workloads

Aspen is a unified accelerator for deep neural network (DNN)-based extended reality perception workloads. Aspen proposes a mixed-precision quantization scheme using the posit datatype to reduce memory usage while maintaining accuracy, a DNN accelerator for mixed-precision posit datatypes, and efficient data prefetching and data layout to minimize data reorganization. The Aspen system-on-chip has an Arm Cortex-M3 CPU, a mixed-precision posit-based DNN accelerator, and 4 megabytes of SRAM partitioned into eight 512 KB banks, connected through a 128-bit-wide interconnect.

Collaborative
Active Project

Indonesia Collaborative SoC Platform

This program is dedicated to the development of a System on Chip (SoC) platform, specifically designed to support learning and research activities within Indonesian academic institutions. The platform serves as an educational and research tool for students, lecturers, and researchers to gain hands-on experience in digital chip design.

Collaborative
Active Project
AHB Qspi architectural design
dwn @ soclabs

AHB eXcecute in Place (XiP) QSPI

The instruction memory in the first tape out of nanosoc was implemented using SRAM. The benefit was the read bandwidth from this memory was very fast, the downside was on a power-on-reset, all the code was erased as SRAM is volatile memory. An alternative use of non-volatile memory would benefit applications where  deployment of the ASIC does not allow, or simply time is not available for programming the SRAM after every power up. 

Reference Design
Active Project
soclabs nanosoc microcontroller framework - 2024
soclabs

nanosoc - baseline Cortex-M0 microcontroller SoC (2024 update)
A small SoC development framework to support easy integration and evaluation of academic developed research hardware such as a custom accelerators or signal processing sub-systems.
Reference Design
Active Project
TSRI Arm Cortex-M55 AIoT SoC Design Platform

TSRI Arm Cortex-M55 AIoT SoC Design Platform
 What is TSRI Arm Cortex-M55 AIoT SoC Design Platform?

The Arm Cortex-M55 AIoT SoC design platform is an AIoT subsystem that allows custom SoC designers to integrate their hardware circuits and embedded software for differentiation. The platform is developed by TSRI (Taiwan Semiconductor Research Institute) to support academic research on SoC design. It's built on the Arm Corstone-300 reference package, featuring the Cortex-M55 CPU and Ethos-U55 NPU.