Die to Die (D2D)

Die to Die ("D2D") interconnects are a class of chip-to-chip interfaces designed for dies integrated within close proximity within a single package, often referred to as System in Package or chiplets/interposer. There are competing interconnect options which vary in the specific of the physical layer ("PHY") and the protocol managed by a controller block the manages the transfers between the two dies. The PHY will need to take account of the specific signal driving of the advanced packaging technology.

The PHY can use either a serial or parallel approach. Using more wires for a parallel interface means more physical connections (pin count) and for small die high-edge usage efficiency and low pin count might be a key driver. In low volume fabrication runs associated with academic tape outs the packaging cost can be significant compared to die fabrication costs and keeping pin counts low can help keep research project costs within reasonable constraints.  If a higher pin count is acceptable the overhead for serialisation/deserialisation can be saved. 

At the PHY level the interface needs to transmit the data, clock and any additional signals needed to orchestrate exchanges. To save pins/paths some encoding schemes encode the clock and additional information, for example error recovery, in the coding scheme along with the data. The transmit/receive logic being a little more complex. 

There are a variety of D2D alternatives which take different approaches to managing the transmission of data over the physical medium from custom proprietary mechanisms to proposed standards such as UCIe and Bunch of Wires. Each alternative has design tradeoffs for integration in a chiplet based system. The choice of interconnect might be determined by a number of factors including the quality of the  System in Package or interposer which should be stated in design rules provided by the vendor. If a project is using die from different suppliers then using a standard interface is beneficial.

The Bunch of Wires specification uses a lower data rate per wire compared to a SerDes implementation but requires more wires. The lower data rates allow use of single-ended signaling and denser wire packing without causing interference and losses in the transmission. A PHY slice either transmits or receives 16 bits of data between two die (Multiple slices can be used to create more throughput). The PHY slice transmits the clock signal with the data.  

The Universal Chiplet Interconnect Express (UCIe) is an alternative standard that looks to cover the full range of physical media, silicon interposer, bridge, RDL fan-out, organic substrate, laminates, etc. but also defines higher level protocol layers. UCIe 1.0 adopted the existing PCIe/CXL high-level protocol to support an easy market entry for chiplets from different vendors. The UCIe standard is more comprehensive in terms of the interconnection concerns it covers but the specification is in multiple layers so simple interconnects can be implemented for example using the lightweight streaming protocol layer.

With the AMBA CHI C2C specification Arm have extended the Advanced Microcontroller Bus Architecture (AMBA) interconnect protocol for chiplets. AMBA supports a non-coherent Advanced eXtensible Interface (AXI) protocol and a Coherent Hub Interface (CHI) protocol. The Chip to Chip (C2C) variant of CHI enables the features of AMBA based systems to be extended across chiplet boundaries with on chip traffic packed into a variety of underlying streaming interfaces including UCIe. 

Arm have committed to deliver an open AXI C2C specification for chiplet interconnect.

The specific signal driving of any advanced packaging technology will impact on the system power cost. The D2D connection must minimise the higher energy/bit cost for data transmission compared to single die on-chip wireless interconnects that have an advantage in energy consumption. The different D2D solutions are compared by a variety of Figure-of-Merit performance indicators such as throughput offered (Gbps/mm) at the energy cost (pJ/b). These performance indicators are dependent on physical implementation such as the trade off in ultimate bandwidth, distance of the line, the characteristic of the interconnect medium, etc. The alternate standard ensure the interconnect meets an agreed level of performance between chiplets.