nanoSoC prototyping with Xilinx(R) PYNQ(R) platform

This example design flow supports the nanoSoC reference design with the Xilinx ZCU104 development board as a target. This FPGA prototyping environment has a large and capable ZYNQ UltraSCALE+ FPGA, and is fully supported out-of-the-box with Xilinx PYNQ development environment support. The PYNQ environment supports scripted control using Python to manage the FPGA overlays, and all through a built-in web-hosted server implemented on the ZYNQ Arm embedded processors that implements a Jupyter Notebook framework to support documentation and example usage.

Configuring the PYNQ platform

Comprehensive instructions for setting up the board are provided on the PYNQ site:

  https://pynq.readthedocs.io/en/v2.7.0/getting_started/zcu104_setup.html

Follow the instructions for setting up the hostname, non-default password, and network parameters, and ensure the (re-booted) system offers network services.

FPGA structuring for SoC test-bench

The approach adopted is to use the ZYNQ processing system configuration to provide clocking and reset control to the SoC "Design under Test" (DUT).

The System-on-Chip design is instantiated at the chip level just inside the pad-ring - to present input/output/tri-state-control unidirectional signals rather than bidirectional/tri-stated I/O-s. Care is taken to ensure that the DUT is built independent of Xilinx system IP so in this example flow, the microcontroller design (nanoSoC in this case) is imported in the form of an external IP component.

The testbench "wraps" the DUT with a "socket" that is built, customized to the SoC design using the standard Xilinx Vivado "Block Design" IPXact design capture and tools, to include any specific peripherals - a UART communications channel in this case, plus generic General Purpose Input Output (GPIO) control ports to monitor or stimulate the IO ports.

The Arm-based ZYNQ processing subsystem is completely independent of the SoC DUT but provides the master clock for the device, which can be reconfigured in the Vivado editor. [Set to 20MHz for basic functional testing in the example implementation flow]

FPGA build scripts

FPGA building of nanoSoC can be done directly using the makefiles by using the command:

make build_fpga FPGA=zcu104 ACCELERATOR=yes

If you have yet to include an accelerator in the design then you can set ACCELERATOR=no

This will run through the build scripts, the exact flow can be found in the makefile.fpga file here. The steps are:

• package_socket - this packages the FPGA socket as a stand-alone IP. The socket captures communication and I/O from nanoSoC and gives an AXI subordinate to the Zynq processing system
• package_nanosoc - this packages nanoSoC as a stand-alone IP. As mentioned previously, this is done at the chip level (just below the pad level)
• build_nanosoc_design - builds the block structure shown previously, connecting the Zynq PS, socket and nanoSoc together
• output_nanosoc_design - takes the output .xsa file and unzips it to the output directory (nominally: imp/fpga/output/zcu104/overlays)

Target board specific pin map and timing constraints are accessed from the nanosoc_tech/fpga/targets/pynq_zcu104 directory

The overlay and notebook output files are copied out to the directory:

  imp/fpga/output/zcu104/overlays

These files are then ready for use as Xilinx PYNQ programmable logic overlays.

FPGA programming

The PYNQ board, when successfully configured and connected to the network can be mounted as a file system and logged into from a browser.

The build scripts generate both the configuration bit-file (.bit) and hardware description (.hwh) files in the directory:

   imp/fpga/output/zcu104/overlays

(default names of nanosoc_chip.bit and nanosoc_chip.hwh)

Simply copy the imp/fpga/output/zcu104/overlays sub-tree in the PYNQ board pynq/overlays/ directory

Pynq Python Scripts

You can access the pynq environment over ssh and run python scripts directly in the pynq environment.

To enable the pynq environment run:

source /etc/profile.d/pynq_venv.sh 
source /etc/profile.d/xrt_setup.sh 
source /etc/profile.d/boardname.sh 

We have some example python scripts that are used for the nanoSoC CI/CD here

Jupyter Notebook interaction

You can also run Jupyter notebooks in the pynq environment using the instructions here:  https://pynq.readthedocs.io/en/v2.7.0/getting_started/zcu104_setup.html

It should be possible to connect and log into the PYNQ server from a web browser, and select the upload any jupyter notebookts

Select the ipynb notebook document and this will allow the overlay files to be loaded, checked and run to communicate with the MCU in the FPGA design (through a serial communications driver in this case):