megaSoC Prototyping using HAPS-SX

The example design flow developed and described here targets a HAPS-SX system. HAPS is a modular, high capacity and high performance FPGA-based system. These systems are targeted for ASIC prototyping and comprise of multiple FPGA boards combined into 1 system. At SoC Labs, a HAPS-SX system with an AMD-Xilinx Virtex UltraScale+ VU19P FPGA, which has 8,938K logic cells, and a total of 90 Mb BRAM is being used to develop megaSoC.

Connecting to the HAPS system

FPGA block design for SoC test-bench

The above image shows the block diagram for the FPGA debug environment. This includes a JTAG to AXI component, which uses the Xilinx Virtual Cable to interface with the JTAG side.  tcl commands are used to write to that AXI interface (as seen here). This AXI interface then drives: an UART component, JTAG component, and an FT1248 component. The UART is connected to the UART peripheral within MegaSoC, and the JTAG is connected to the DAP-lite that is used to debug the Cortex A53. The FT1248 component connects to the ADP controller in megaSoC.

The ADP controller was originally created as an easy to use debugger for the nanoSoC. It takes a ASCII characters as input and generates AHB-lite commands to the SoC. The addition of the ADP controller in megaSoC may only be temporary as we assess it's suitability for this full AXI system. But this does however enable reuse SoC Labs resources and a known use case for debugging in FPGA.

FPGA build scripts

FPGA Programming

SoC emulation and programming