corstone 1000 a53/a55

Corstone 1000 supports development of secure Linux-capable SoCs designs. It has achieved Platform Security Architecture (PSA) Level 2 Certification making it an ideal reference design for edge based compute tasks.

SSE-710 compute subsystem that combines Cortex®‑A and Cortex®‑M processors with an integrated TrustZone and Secure Enclave. The Secure Enclave utilises an isolated M0+ processor, with dedicated memory, and peripherals, such as timers and watchdogs, which provide a hardware Root of Trust. On system power up, the Secure Enclave is used as the initial system boot target. Firmware running on the Secure Enclave is isolated via hardware firewalls to provide the necessary security. It supports a socket into which a Crypto Accelerator can be integrated.

The compute subsytem combines a host processor, usually a Cortex®‑A (up to 4 cores) processor with two optional Cortex®‑M, or other compute managers (External Systems). The CoreLink GIC-400 Generic Interrupt Controller provides interrupt handling for the host A class processor. The reference design provides the interrupt maps of the Host System and Secure Enclave system. 

Firewalls provide Hardware address protection of the  Host processor's address space.  Message Handling Units (MHUs) are used to communicate between the different compute systems in the SSE-710 subsystem. Each MHU is a unidirectional channel, with a pair of MHU separating communication between each master processing node. 

The SSE-710 subsystem manages interrupt router of interrupts from shared peripherals to the interrupt controller of the desired compute system.

CoreLink NIC-450 AXI based network interconnect. It includes the ADB-400 AMBA® Domain Bridge an asynchronous bridge between two components or systems that can be in a different power, clock, or voltage domains. The interconnect can be tailored to the specific SoC design using the Socrates™ tool to aid the creation of valid configurations.

Power management within the SoC is provided by the CoreLink PCK-600 Power Control Kit which provides system power control elements (including the LPD-500 Low Power Interface Distributor)

A common debug infrastructure supports single and multi-system debug, by self-hosted and external debug agents. CoreSight SoC-600, CoreSight SDC-600 Secure Debug Channel and CoreSight STM-500 System Trace Macro form the basis of the SoC debug infrastructure.

The Corstone 1000 provides the core compute system IP for the SoC design to which needs to be added the necessary memory and peripheral subsystem components to make the target SoC design.