Reference Design Comparison Table
| Title | nanoSoC |
|---|---|
| Class | Entry |
| Reference Design | nanoSoC |
| Staffing | Single student / academic |
| Time Scales | 6 months to 1 year |
| Model Forms | small |
| Tape Out / Package and Board Costs | From 10k Euro |
| Processor(s) | M0 |
| Processor(s) (speed) | <250 Mhz |
| Data Rates / On Chip Comms | <2.5 Gbps |
| Data Rates / Off Chip Comms | <50 Mbps |
| On Chip Memory Requirements | 32KB to sub MB |
| Virtual Prototype Environment | Xilinx ZCU104 |
| Tape Out Node | 65nm |