What is TSRI Arm Cortex-M55 AIoT SoC Design Platform?

The Arm Cortex-M55 AIoT SoC design platform is an AIoT subsystem that allows custom SoC designers to integrate their hardware circuits and embedded software for differentiation. The platform is developed by TSRI (Taiwan Semiconductor Research Institute) to support academic research on SoC design. It's built on the Arm Corstone-300 reference package, featuring the Cortex-M55 CPU and Ethos-U55 NPU. The platform is equipped with popular peripherals such as camera input, video output, and audio in/out, enabling support for a wide range of applications.

Features Highlights

• Silicon proven - 16nm reference design
• System ready - EVB, bare-metal BSP, sample systems for AI applications (Yolo-fastest object detection and keyword spotting)
• FPGA prototyping system available
• Lower the technical barrier of custom SoC design
• Accelerate time to tape-out/publication

SoC Specification

SoC Memory Map

The memory map follows the guide of "Memory map overview for Corstone™ SSE-300". (https://developer.arm.com/documentation/100966/1127/Arm--Corstone-SSE-300-FVP/Memory-map-overview-for-Corstone-SSE-300)

Users' HW circuits design, SoC integration and simulation

Users can design their own HW circuits to accelerate computing for specific application processing, such as object detection, generative AI, cryptography, and DNA sequencing data analysis. Users can replace the built-in Ethos-U55 NPU with thier own NPU if necessary. Their HW circuits must have an AMBA interface to be integrated into the TSRI Arm Cortex-M55 AIoT SoC design platform.

Users can easily integrate their own HW circuits into the TSRI Arm Cortex-M55 AIoT SoC design platform and start the whole SoC simulation by following these steps.

1. Before integrating users' HW circuits, run out-of-box testing to ensure the environment for SoC integration and whole SoC simulation is installed properly.
2. Replace the dummy RTL code with users' own RTL code of HW circuits. Make sure the RTL code is well verified by simulation before going to this step. It is highly recommended to use Verification IP for AMBA bus interface compliance checks.
3. Develop the embedded SW/FW based on the given environment and sample code, which is part of TSRI Arm Cortex-M55 AIoT SoC design platform. Arm Development Studio will be used for SW/FW development.
4. Change to working mode from test mode by undefine a parameter.
5. Run simulation. Cadence Xcelium Logic Simulator or Synopsys VCS will be used for simulation. Synopsys Verdi will be used for debug.

FPGA Prototyping

It's almost impossible to fully verify the function of the whole SoC by simulation only due to the long simulation time. FPGA prototyping will be used to speed up verification and for early software bring-up as well. The FPGA prototyping system allows designers to implement and test their designs on reconfigurable FPGA hardware before committing to final silicon. TSRI use Arm MPS3 FPGA Prototyping Board for FPGA prototyping of Arm Cortex-M55 AIoT SoC design platform. A camera module and a display module were developed by TSRI and added to the Arm MPS3 FPGA Prototyping Board for real-time video application development.

Fig. 1- FPGA Prototyping System

Synopsys Synplify Premier and Xilinx Vivado will be used for FPGA prototyping.  The maximum clock rate of this FPGA prototyping system is 50MHz. The FPGA utlization is as follows.

Fig. 2- FPGA Utilization of TSRI Arm Cortex-M55 AIoT SoC design platform

16nm Reference Design RTL to GDS(R2G) Implementation and Verification

A 16nm reference design was taped out for manufacturing. After the sign-off of RTL code of the whole SoC (that means RTL code is well verified either by simulation or FPGA prototyping), TSRI started R2G implementation and verification. Synopsys Design Compiler was used for the logic implementation (Logic Synthesis). Cadence Innovus was used for the physical implementation (APR/Automatic Placement & Routing). Synopsys PrimeTime was used for the static timing analysis (STA). The complete SoC design flow is illustrated as follows.

Fig. 3- SoC Design Flow

The layout of the taped out design is as shown below.

Fig. 4- SoC Layout

The  statistics of the 16nm reference design implementation are as shown below.

The runtime for the physical implementation is 44 hours in terms of real time and 326 hours in terms of CPU time. The multi-core option was turned on when running EDA tools, with the core (thread) number set to 64. The elapsed time for each stage is shown below.

Fig. 5- Runtime of each stage of the physical implementation

ASIC and Evaluation Board(EVB)

The manufactured chip was tested on EVB TSRI developed. The validation system worked well. CPU, NPU and all periherals including video and audio in/out worked properly.

Fig. 6- The Silicon

Fig. 7- The EVB

Sample Systems for AI applications

• Yolo-fastest object detection
  • Ref: Object Detection Code Sample
• KWS (KeyWord Spotting)
  • Ref: Keyword Spotting Code Sample

Using TSRI Arm Cortex-M55 AIoT SoC Design Platform

Taiwan's research teams are all eligible to use the TSRI Arm Cortex-M55 AIoT SoC Design Platform. Overseas research teams may access the TSRI SoC design platform through collaborations with Taiwan's research teams. This is upon request and requires TSRI's approval. Since the platform contains Arm IP, the professor leading the research team must be an AAA (Arm Academic Access) member. Membership is free of charge. Refer to the following link for details of the AAA program.

https://www.arm.com/en/resources/research/enablement/academic-access

The TSRI Arm Cortex-M55 AIoT SoC Design Platform can only be used in the TSRI cloud. Users' data cannot be downloaded to protect the valuable silicon IP accessible in the cloud. The overview of TSRI's cloud is shown below.

Fig. 8- TSRI's EDA Cloud for SoC design

Future Work

The silicon we currently have does not include a PLL. We have integrated the PLL into the TSRI Arm Cortex-M55 AIoT SoC design platform and have been working on a new reference design, which will be taped out in 2025. Universities' HW circuits may be integrated into the new reference design. The options of the target 16nm technology will be slightly modified to comply with the TSMC University FinFET program offering. Refer to the following link for details of the TSMC University FinFET program.

https://www.tsmc.com/english/dedicatedFoundry/services/university_program

After that, TSRI will collaborate with partners from industry and academia to develop SoC design training courses based on the new reference design.