Competition 2025
Competition: Hardware Implementation

Neural Activity Processor

Stroke and epilepsy are among the most common debilitating neurological conditions, with a worldwide prevalence of 100 million people (World Stroke Organization, 2022) and 50 million people (World Health Organization, 2024), respectively. Present-day approaches for treating neurological and neurosurgical conditions include physiotherapy, pharmacological treatment, surgical excision, and interventions such as deep brain stimulation. While it is clear that the nervous system transmits information via spikes emitted by individual neurons, no therapeutic tool attempts to target the CNS at that spatiotemporal resolution. 

We aim to develop a miniature integrated device for the parallel recording, analysis, and control of multiple spiking neurons to enable neuronal-level therapeutics. Coupled with intracortical recording and stimulation arrays, the proposed CMOS device will be used to alleviate disease symptoms in a mouse model.  By implementing this device as an SoC we introduce a wider dynamic neural input into the model and enable remote neuronal-level therapeutic interventions.

Two strategies will be employed: a “local circuit” approach, tailored for focal epileptic seeds; and a “cortical bypass” approach, designed to supplement lost functions following focal stroke. The same device will support both applications.

Implementing this challenging device demands a well-structured design comprised of custom analysis, signal processing, and control components interconnected around and with an ARM central processing unit core. Each of the components, except for the CPU, will be custom-made to ensure tailored performance. The neural signals — the real-world stimuli — will be recorded and transmitted under the control of a sampler component, analyzed by a co-processor and saved by an SD controller to an SD card. The co-processor will issue an interrupt to the CPU when stimulation is needed and the request will be sent to a stimulation controller to trigger a stimulus. The CPU will allow this feedback mechanism to operate as planned, resulting in a closed-loop Neural Activity Processor. Future translational work will adapt the technology to be developed in this project to human applications.

Project Milestones

Architectural DesignGetting StartedSpecifying a SoCdata modelIP SelectionUniversal Verification Methodology
Behavioural DesignBehavioural ModellingGenerate RTLRTL VerificationSimulation
Logical DesignTechnology SelectionSynthesisDesign for TestLogical verification
Physical DesignFloor PlanningClock Tree SynthesisRoutingTiming closurePhysical VerificationTape Out
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