Aspen: Unified Accelerator for Extended Reality

An SoC for Extended Reality (XR) applications utilising an M3 CPU core with a mixed-precision posit-based DNN accelerator and 4 megabytes of SRAM partitioned into eight 512 KB banks, connected through a 128-bit-wide interconnect. The custom accelerator uses a mixed-precision quantization scheme and the posit datatype to reduce memory usage while maintaining accuracy to implement a perception pipeline that exclusively leverages DNNs for Visual Inertial Odometry, gaze estimation and scene understanding.

The matrix unit is a 16×16 systolic array of processing elements (PEs) that accelerates convolutions and matrix-matrix multiplications. Each PE performs one multiplyadd operation. The matrix unit decodes 8-bit posit (Posit8) inputs, performs computation in the decoded representation, and then accumulates in decoded 16-bit posit (Posit16). 

The vector unit contains a 4-stage pipeline for matrix-vector multiplication, element-wise, and nonlinear operations on 16-word-wide data. Vector unit stages are selectively activated to perform various functions, and with the matrix unit, support all operations in the XR perception workloads.

It operates at a maximum frequency of 360 MHz and a nominal voltage of 0.85V using the Intel 16nm foundry node.