IMPLEMENTATION OF FIXED TIME BASED TRAFFIC LIGTH SYSTEM USING FPGA WITH VERILOG HDL.
This Project is to develop traffic light system that can reduce traffic congestion with the aid of counters for each lane and acts wisely with the intersection in real time based with a fixed time constrain, include both hardware and software requirements using SOC FPGA technology with fundamental specification for the Register Transfer Level (RTL).
Project Milestones
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FPGA SoC prototyping with Xilinx(R) PYNQ(R) platform
Target Datefamiliarize with the CAD tool.
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Architectural Design
Design FlowTarget Datestructural design of the project
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Behavioural Design
Design FlowTarget Datefunctional design of the system
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Simulation
Design FlowTarget Datethe system imitating the rea world scenarios.
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Behavioural Modelling
Design FlowTarget Dateabstract representation of the system
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Design for Test
Design FlowTarget Dateverification of the system based on the requirements.
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Milestone #7
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Milestone #8
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Milestone #9
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Milestone #10
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Milestone #11
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Milestone #12
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Milestone #13
Target Date
Team
Project Creator
AFOLAYAN, ABDULSAMAD
STUDENT
at Obafemi Awolowo University
Research area: FIELD PROGRAMMABLE GATE ARRAYS
Cortex-A7
Hardware design
Submitted on
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