UK System on Chip Design Contest 26-27

Build your SoC design skills with funding for a tapeout and get technical support from the SoC Labs team along the way! 

The  UK System-on-Chip Design Accelerator announced under the  UK AI Hardware Plan has received funding from EPSRC to help support SoC design projects undertaken by individuals and teams in UK university/research institutions. As part of the activity, we are pleased to announce a UK specific design contest for 2026/2027. 

The competition follows the usual SoC Labs methodology of two separate tracks, 

• an education/collaboration aimed at those with little SoC design skills and no prior tapeout experience,
• a hardware design track focused on novel designs for those with some previous SoC design experience. 

Designs can target any functionality/application but must be integrated into a System on Chip using one of SoC Labs reference designs. Contestants will receive ongoing support from the SoC Labs team throughout the competition.

The UK System-on-Chip Design Accelerator has the aim of addressing challenges in UK workforce development, especially the gap between core foundation skills provided by traditional academic teaching and the practical application skills needed by industry. The aim of the programme is to develop talent by working on industrially relevant, real-world chip and artificial intelligence design challenges.

Eligibility

The contest is open to individuals or research groups with members working within a university/research institution located in the United Kingdom. These projects must be led by a staff member at a UK University or research institute, however collaboration with other UK or international partners is allowed. Project teams can be of any size and can include undergraduate students, MSc students, PhD students, post-doctoral researchers, academics and other technical staff. Multiple applications from the same institution can be submitted and supervisors can support more than one postgrad student. If collaborating with other institutions, the lead institution is expected to undertake their own due diligence when involving any partner organisation.

You will be ineligible for funding if you have previously received funding for tapeout through a SoC Labs competition. Applicants from the University of Southampton are ineligible due to it being the host for SoC Labs and the UK System-on-Chip Design Accelerator. Submitted projects must be part of a System on Chip using one of SoC Labs’ reference designs.

Getting Involved

SoC Labs contests support two alternate tracks:

Collaboration/Education track

Collaboration/Education track focuses on developing SoC design skills within the academic community and broadening the range of institutions undertaking SoC design activity. This track is ideal for a PhD, Masters or group of undergraduate students or an academic that is new to computer engineering. The focus is not on the hardware design challenge but on how people develop community collaborations and clearly show institutional and individual skill development in SoC design. It does not require a unique hardware design and can reuse design from other groups either for a new application or simply as a skills development activity; even forming a collaboration to re-purpose open-source IP into community re-usable IP. 
Groups interested in working with other prospective collaborators should post details of their project idea to SoC Labs, including enough detail of progress to date to help others engage. SoC Labs will try and help with the formation of shared community hardware projects. Alternatively, academics involved in teaching SoC design may submit a project summary detailing their approach, including benefit for the community. 

Hardware Implementation track

Hardware Implementation track focuses on innovative design. It is to engage with researchers and research teams who are looking to develop novel and new SoC designs and design methods and techniques. The focus of this is on the hardware design challenge(s) and will be judged based on the novelty, technical innovation, quality of implementation, and impact. There is no restriction on the topic of the project. 

People taking part in the competition will create a new ‘Competition’ project on the SoC Labs website. A project has a timeframe and uses the two other significant aspects of a SoC development, the selection of technology or IP blocks that make up the SoC and the various stage and steps in the design flow that are followed from specification through to final instantiation of the system. We have a growing number of example-flows using both industry EDA tools and open-source alternatives. To make it easier to engage in the contest we have created reference SoC designs. 

Entry submission and applying

Entry is via the SoC labs website. You will need to sign up to SoC Labs as described on the home page. 

Submissions take the form of a project summary of no more than 350 words, written in English. For those interested in the Collaboration/Education track you should consider providing a set of milestones that help show how your SoC design skills development project will be demonstrated.

Once logged in, submit your project summary via the My Contributions menu located in the top-right corner of the site. Select Add Competition Project to create your competition entry.

Alternatively: Collaboration/Education tracks can use this link to create an entry; Hardware Implementation tracks can use this link to create an entry.

Key Dates

Contest Opens: 22nd September 2026

Projects should post incremental updates of their progress to be published at least monthly, to help illustrate project journeys. 

Projects should be submitted to be included in the judging: February 28th, 2027

Submitted projects will be judged: 31st July 2027

Tapeout shuttles will be confirmed after projects are judged.

Winning Projects

Where rewards or prizes are given, they will be for the best project(s) in each track, as determined by the judging panel using the judging criteria below. Rewards include funding to support a tapeout, all contestants will also receive ongoing support from the SoC Labs team throughout the competition. Winning entries will have some or all of the cost of tapeout covered subject to total area and process node. Tapeout nodes are expected to be between 65 nm and 7 nm, but other options may be considered.

Judging

The judging criteria will centre on how effectively (a) teams achieve self-defined goals and (b) the extent to which the journey has the potential to assist other research groups around the world to push research and development boundaries. The contest theme is open to all manner of research topics, without prescription. 

The judging panel will consist of domain experts and will include at least 1 member from previous design contests. Judgement will be based on your published project on the SoC labs website.

Collaboration/Education track Criteria:

The Collaboration/Education track recognises projects that develop System-on-Chip design capability, support learning, and help others engage with SoC design. The focus is not on the technical novelty of the hardware itself, but on the educational value of the project journey, the development of skills, and the extent to which participants document and share their experiences with the wider community.

• Skills Development and Learning Journey (35%): How effectively participants demonstrate growth in their SoC design knowledge, skills, and confidence throughout the competition.
• Project Execution and Achievement of Goals (25%): How effectively the team defines, plans, and achieves its own objectives, including evidence of progress and adaptation to challenges.
• Knowledge Sharing and Community Benefit (15%): The extent to which the project helps others learn or engage with SoC design through the sharing of resources, experiences, tools, or lessons learned.
• Tapeout Readiness (10%): Maturity of the implementation flow and evidence that the design could successfully progress towards fabrication. 
• Documentation and Communication (10%): Quality and clarity of project reporting, progress updates, technical communication, and presentation of outcomes
• Reflection and Future Impact (5%): Evidence of critical reflection on the project journey, lessons learned, and how the experience may benefit future work.

Hardware Track Criteria:

The Hardware Implementation track recognises innovative and technically excellent SoC designs, IP blocks, design methodologies, and hardware research outputs.

• Technical Innovation (30%): Novelty and originality of the design, methodology, architecture, or application being developed. 
• Quality of Implementation (25%): Engineering quality, robustness, architectural clarity, and effectiveness of integration within a complete SoC environment.
• Verification and Validation (15%): Evidence that the design functions correctly and has been appropriately tested, evaluated, or benchmarked. 
• Impact and Relevance (15%): Potential benefit to research, industry, education, or society, and the significance of the problem being addressed. 
• Tapeout Readiness (10%): Maturity of the implementation flow and evidence that the design could successfully progress towards fabrication. 
• Communication and Documentation (5%): Quality of technical reporting, design documentation, architecture descriptions, and reproducibility information. 

Equality, Diversity and Inclusion Statement

The UK SoC Design Contest is committed to fostering an inclusive, welcoming, and respectful environment for all participants. We believe that excellence in research and engineering is strengthened by diversity of backgrounds, experiences, perspectives, and ideas.

We encourage participation from individuals and teams across all UK universities and research institutions, including those with limited prior experience in System-on-Chip design. We particularly welcome applications from groups that are currently under-represented within engineering, computing, and semiconductor design disciplines.

The competition has been structured to support a broad range of participants through both the Collaboration/Education and Hardware Implementation tracks, recognising that valuable contributions can arise from skills development, community building, teaching innovation, as well as technical research and hardware development. 

Judging will focus solely on the above criteria. Participants will be treated fairly and equitably regardless of age, disability, ethnicity, gender identity, nationality, religion or belief, sexual orientation, socio-economic background, career stage, institution, or any other protected characteristic. The judging panel will be required to have completed unconscious bias training. 

Assessment and judging will be evidence-based and aligned to the published competition criteria. Panel members will be asked to evaluate submissions on the quality of the work presented rather than the reputation of individuals, research groups, or institutions. Judges will be encouraged to consider the context in which projects were undertaken, including participants' prior opportunities, experience, available resources, and institutional support. In particular, the panel should recognise achievement relative to starting point, especially where projects demonstrate significant skills development, capacity building, or engagement from institutions with limited prior experience in System-on-Chip design

Through this competition, we aim to help broaden participation in semiconductor and SoC design, support the development of future talent, and strengthen the UK's diverse and collaborative hardware design community.

We are committed to supporting equality, diversity and inclusion in accordance with UKRI and EPSRC principles and to ensuring that opportunities arising from the competition are accessible to the widest possible range of participants.

IP statement

Teams are encouraged to share their designs where relevant. The default position is that third parties should be able to recreate the outcomes of any projects submitted to the competition. If there are some aspect of your design that is sensitive, you may submit details of the method rather than the IP block detail itself. Any IP statements and conditions of use should be made clear. Participants retain ownership of any intellectual property generated through their projects. 

More details:

We may be posting some additional details here and responding to any frequently asked questions. You are welcome to add any questions by using the comment field below.

Any publication stemming from this EPSRC funding need to acknowledge the UK System-on-Chip Design Accelerator by including the text “This work was supported by the Engineering and Physical Sciences Research Council [grant number UKRI4096]."