IMPLEMENTATION OF FIXED TIME BASED TRAFFIC LIGTH SYSTEM USING FPGA WITH VERILOG HDL.
This Project is to develop traffic light system that can reduce traffic congestion with the aid of counters for each lane and acts wisely with the intersection in real time based with a fixed time constrain, include both hardware and software requirements using SOC FPGA technology with fundamental specification for the Register Transfer Level (RTL).
Project Milestones
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FPGA SoC prototyping with Xilinx(R) PYNQ(R) platform (151)Target Date
familiarize with the CAD tool.
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Architectural DesignDesign FlowTarget Date
structural design of the project
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Behavioural DesignDesign FlowTarget Date
functional design of the system
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SimulationDesign FlowTarget Date
the system imitating the rea world scenarios.
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Behavioural ModellingDesign FlowTarget Date
abstract representation of the system
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Design for TestDesign FlowTarget Date
verification of the system based on the requirements.
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Milestone #7Target Date
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Milestone #8Target Date
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Milestone #9Target Date
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Milestone #10Target Date
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Milestone #11Target Date
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Milestone #12Target Date
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Milestone #13Target Date
Team
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Project Creator
AFOLAYAN, ABDULSAMAD
STUDENT
at Obafemi Awolowo University
Research area: FIELD PROGRAMMABLE GATE ARRAYS
Cortex-A7
Hardware design
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