Competition 2024
Competition: Collaboration/Education

IMPLEMENTATION OF FIXED TIME BASED TRAFFIC LIGTH SYSTEM USING FPGA WITH VERILOG HDL.

This Project is to develop traffic light system that can reduce traffic congestion with the aid of counters for each lane and acts wisely with the intersection in real time based with a fixed time constrain, include both hardware and software requirements using SOC FPGA technology with fundamental specification for the Register Transfer Level (RTL).

Project Milestones

  1. Architectural Design

    Target Date

    structural design of the project

  2. Behavioural Design

    Target Date

    functional design of the system 

  3. Simulation

    Design Flow
    Target Date

    the system imitating the rea world scenarios.

  4. Behavioural Modelling

    Target Date

    abstract representation of the system 

  5. Design for Test

    Design Flow
    Target Date

    verification of the system based on the requirements.

  6. Milestone #7

    Target Date
  7. Milestone #8

    Target Date
  8. Milestone #9

    Target Date
  9. Milestone #10

    Target Date
  10. Milestone #11

    Target Date
  11. Milestone #12

    Target Date
  12. Milestone #13

    Target Date

Team

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Project Creator
AFOLAYAN, ABDULSAMAD

STUDENT at Obafemi Awolowo University
Research area: FIELD PROGRAMMABLE GATE ARRAYS

Technology

Cortex-A7 Cortex-A7

Submitted on

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