Member for
2 months 3 weeks
Name
Naveen Bhukya
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Custom CNN models
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Projects

Title Updated date Comment count
High Capacity Memory Subsystem Development 34 minutes 33 seconds ago 35

Articles

Interests

Design Flow

RTL Verification

RTL Verification

Universal Verification Methodology

Universal Verification Methodology

Physical Verification

Physical Verification

Technology

SoC Labs Accelerator Wrapper

SoC Labs Accelerator Wrapper

SoC-400

SoC-400

Authored Comments

Subject Comment Link to Comment
Interested in Collaboration for the project

Hi

My self I have Naveen 

Area of interest:Verification , RTL Desgin ,Physical desgin .

Skills:verilog,system verilog ,UVM,Python

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#71

Comments

Hi,

just added a comment on Todays call:

High Capacity Memory Subsystem Development | SoC Labs

In it 'A discussion on the verification strategy occurred and we agreed that the second meeting in December would be dedicated the verification'. 

Do you think you can get involved with this and help determine the verification planning for the project?

We look forward to hearing from you.

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