Member for
8 months 1 week
Name
Research Area
FIELD PROGRAMMABLE GATE ARRAYS
Role
STUDENT
Points
120
SoC Labs Roles
Registered User
Projects
| Title | Updated date | Comment count |
|---|---|---|
| IMPLEMENTATION OF FIXED TIME BASED TRAFFIC LIGTH SYSTEM USING FPGA WITH VERILOG HDL. | 1 month ago | 0 |
Articles
Interests
Technology
Authored Comments
User statistics
My contributions
:
10
My comments
:
0
Overall contributor
:
#13
Add new comment
To post a comment on this article, please log in to your account. New users can create an account.