Skip to main content
SoC Labs

the global community for arm-based projects

  • Home
  • About
  • Organisations
    • Academic Institutions
    • Industry Supporting
      • Semiconductor Education Alliance
      • Other Industry Partners
    • Known Good Dies
  • Projects
    • Reference Design
      • Active
      • Case Study
    • Competition
      • Collaboration/Education
      • Hardware Implementation
      • Chiplets
    • Collaborative
      • Active
      • Request of Collaboration
      • Case Study
    • All
  • Technology
    • Communication
      • On-Chip Communication
        • Advanced Microcontroller Bus Architecture
        • CoreLink NIC-400
        • CoreLink NIC-450
        • CoreLink CCI-400
        • CoreLink CCI-500
        • CoreLink CCI-550
        • CoreLink ADB-400
        • XHB-400: AXI4 to AHB-Lite Bridge
      • Wired Off-Chip Communications
        • Die to Die (D2D)
        • Host-IO
        • SPI/QSPI
        • FT1248
        • I2C/I3C
        • UART
      • Wireless off-chip communication
        • Bluetooth LE
        • Near Field Communication (NFC)
        • RFID
        • Wi-Fi
    • Processors
      • Cortex-A Series
        • Cortex-A53
        • Cortex-A35
        • Cortex-A34
        • Cortex-A32
        • Cortex-A7
        • Cortex-A5 (UP and MP)
      • Cortex-M Series
        • Cortex-M55
        • Cortex-M33
        • Cortex-M23
        • Cortex-M7
        • Cortex-M4
        • Cortex-M3
        • Cortex-M0+
        • Cortex-M0
      • Cortex-R Series
        • Cortex-R52
        • Cortex-R8
        • Cortex-R5
    • Accelerators
      • Ethos-U55
      • Mali-G52
      • SoC Labs Accelerator Wrapper
      • Mali-G31
      • Mali DDKs
      • Bifrost DDKs
      • Bifrost Android Renderscript
    • System Controllers
      • Interrupt Controllers
        • GIC-500 General Interrupt Controller
        • GIC-400 General Interrupt Controller
        • PL192 Vectored Interrupt Controller
      • TZC-400 TrustZone Address Space Controller
      • L2C-310 Level 2 Cache Controller
      • MMU-500 System Memory Management Unit
      • BP140 AXI Memory Interface
      • BP141 TrustZone Mem. Adapter
      • PCK-600 Power Control Kit
    • Security
      • Physically Unclonable Function
      • True Random Number Generator
    • Corstone Subsystems
      • Corstone 101 for m0/m3
      • Corstone 102 for M23
      • Corstone 201 for m33
      • Corstone 300 for M55
      • Corstone 500 for A5
      • corstone 1000 a53/a55
    • Peripherals
      • PL011 UART
      • PL022 SPI - Synchronous Serial Port
      • PL031 RTC Real Time Clock
      • CoreLink DMA-230
      • CoreLink DMA-330
      • Corelink DMA-350
    • Debug & Trace
      • SoC-600
      • SoC-400
      • SDC-600
      • STM-500
      • System Trace Macrocell
      • Trace Memory Controller
    • Tools & Models
      • COIL-3D: A CAD Tool for the Optimisation of Inductive Links in 3D-ICs
      • Socrates Interconnect tool
      • Arm DS-Gold
      • Virtual system models
      • MDK V8-M
      • Fused
  • Design Flow
    • Architectural Design
      • Getting Started
      • Specifying a SoC
      • IP Selection
        • IP Library Structure
      • data model
      • Universal Verification Methodology
    • Behavioural Design
      • Behavioural Modelling
      • Generate RTL
      • RTL Verification
        • FPGA SoC Prototyping design flows
        • nanoSoC prototyping with Xilinx(R) PYNQ(R) platform
        • milliSoC prototyping with ARM MPS3 platform
        • megaSoC Prototyping using HAPS-SX
      • Simulation
    • Logical Design
      • Technology Selection
        • Standard Cell Libraries
        • Memory generators
      • Synthesis
      • Design for Test
      • Logical verification
    • Physical Design
      • Floor Planning
      • Clock Tree Synthesis
      • Routing
      • Timing closure
      • Physical Verification
      • Tape Out
    • Post Silicon
    • Example flows
      • Accelerator Wrapper Flow
      • Continuous Integration and Deployment for verification
      • SoC Design Contest 2023 - now deprecated
        • Project Structure
        • Specifying your IP
        • Accelerator Design Flow
        • Algorithmic Modelling Design Flow
        • Basic System Accelerator Integration Verification
  • Interests
    • Hardware design
      • Low power design
      • RF and Analog Design
      • Packaging
    • Machine Learning
      • PyTorch
      • TensorFlow
      • hls4ml
    • Student Area
      • Getting Started with SoC Labs
      • Hardware Design Environment
    • Software
      • Debugging
      • Firmware
      • SystemC®
    • SoC Labs site
      • Moderation
      • Site structure
  • News
  • Reference Design

User account menu

  • Log in
Icon for Home Icon for About Icon for Organisations Icon for Projects Icon for Technology Icon for Design Flow Icon for Interests Icon for news Icon for Reference Design
Placeholder
Member for
3 months
Name
Falah
Research Area
Computing
Role
Student
SoC Labs Roles
Registered User
anglia ruskin university logo

Projects

Articles

Interests

Getting Started with SoC Labs

Getting Started with SoC Labs

Low power design

Low power design

Design Flow

IP Selection

IP Selection

Technology

Arm DS-Gold

Arm DS-Gold

Authored Comments

User statistics

My contributions
:
0
My comments
:
0

Add new comment

To post a comment on this article, please log in to your account. New users can create an account.

Footer

  • Contact
  • Feedback
  • Terms of Use

University of Southampton