DATE 25-26 SoC Design Contest

At DATE 24 we launched the “Understanding Our World” SoC design contest for 2024/25 and we are pleased to return to DATE to delivery the workshop  "SoC Labs: The academic community for System on Chip Development"  where we will present prior projects from around the world and the progress they have made to taping out their SoC designs. For the year ahead we are pleased to announce an new contest.

Background:

SoC Labs has already supported projects with the community that have developed designs that use custom acceleration for Artificial Intelligence and Machine Learning workloads. This is an ongoing area of interest. We will look to stimulate new functions and kernels that can be computed either on the traditional CPU or new custom acceleration depending on the optimisation of the various SoC design constraints. The various issues of accuracy, energy consumed, latency, area cost, to name need to be traded against each other. In the last year since DATE 24, the “Understanding Our World”, has focused on how real world stimuli can be used in a SoC design to better make sense of the environment around us. 

This year we are looking to encourage projects that support on-device intelligence that can make a real impact in the world we live. This could be in the area such as:

• robotics including all forms of autonomous movement

• something that assists us in our day to day lives or helps assess our health and well being

• that protects the natural environment or manages the buildings and places in which we live and work

• entertains us or allows us to interact with the world around us in new and exciting ways such as with augmented reality

Hopefully it will be something that has a positive effect our daily live and the lifestyles we choose. As engineers it might also be interesting to develop a design that targets a more advanced node for final fabrication.

Getting involved:

As with prior contests, we are planning conference attendance and silicon tape out, activities and we will again support two alternate tracks: 

1. Collaboration/Education track focuses on developing SoC design skills  within the academic community and broadening the range of institutions undertaking SoC design activity. This track is ideal for a PhD, Masters or group of undergraduate students or someone new to computer engineering. The focus is not on the hardware design challenge but on how people develop community collaborations and clearly show institutional and individual skill development in SoC design. It does no require a unique hardware design and can reuse design from other groups either for a new application or simply as a skills development activity; even forming a collaboration to re-purpose open-source IP into community re-usable IP. 

   Groups interested in working with other prospective collaborators should post details of their Arm-based project idea to SoC Labs, including enough detail of progress to date to help others engage.  SoC Labs will try and help with the formation of shared community hardware projects.  Alternatively, academics involved in teaching SoC design may submit a project summary detailing their approach, including benefit for the community. 

    

2. Hardware Implementation track focuses on  innovative design. It is to engage with researchers and research teams who are looking to develop novel and new SoC designs and design methods and techniques. A SoC project should demonstrates how compute (including custom acceleration) makes use of real world data to show clear impact. There is no prescribed split between capturing the external world stimuli and the more digital custom compute. The design can address one or more of the many areas of interesting issues in handling signal that represent the real world, calibration, accuracy/sensitivity, noise, energy efficiency, novel compute, and many more.  These have different design characteristics and their efficient integration into a SoC design is the focus.  A design should demonstrate some outcome or impact in the real world. It can use any from of stimuli / data from the real world from simple vibrations to complex frame or video. 

   The application area is open and could range from a simple novel sensor with a single signal to a more complex or pixel-based sensor platform requiring highly parallel signal processing. 

This is an online contest with different rewards, including support for conference attendance and silicon tape out, for the different tracks and activity types. The contest is open to universities or research institutes, subject to the eligibility criteria below.

People taking part in the competition will create a new ‘Competition’ project. A project has a timeframe and uses the two other significant aspects of a SoC development, the selection of technology or IP blocks that make up the SoC and the various stage and steps in the design flow that are followed from specification through to final instantiation of the system. We have a growing number of example flows using both industry EDA tools and open-source alternatives. To make things easy for people to engage with the contest we have created reference SoC designs, eg. nanoSoC but you can use others. 

The contest is being supported by the Semiconductor Education Alliance partners. The partners will be assisting the teams and competition in a variety of ways to ensure the community are successful. The best entries will be supported by Arm to attend DATE 2025. Arm and other partners will also help develop opportunities to join appropriate ASIC fabrication shuttles and will contribute towards their cost as part of the competition reward. Teams interested in taping-out their designs should include details of their proposed technology and design flow requirements. 

Eligibility Criteria:

Only Arm processor-based designs will be considered.  The Arm Academic Access (AAA) program is open and ready to receive applications from universities and research institutes to provide access a suite of Arm IP to empower your work on Arm. 

The contest is open to research groups with members working within a university/research institution or individual academics involved in SoC Design teaching. Research groups applications can also be from postgraduate students, but applications from postgrads should be supported by a senior member of staff in the same institute who is supervising them. Multiple applications from the same institution can be submitted and supervisors can support more than one postgrad student. 

Entry submission and applying: 

Entry is via this site. You will need to sign up to SoC Labs as described on the home page. 

When you are logged in, a Project summary should be submitted via the ‘My Contributions’ tab and dropdown at the top right.  You need to use the ‘Add Competition Project’ action.  

Alternatively: Collaboration/Education tracks can use this link to create an entry; Hardware Implementation tracks can use this link to create an entry.

Submissions take the form of a project summary of no more than 350 words, written in English. For those interested in the Collaboration/Education track you should consider providing a set of milestones that help show how your SoC design skills development project will be demonstrated.

Important Dates:

Competition opens: March 31st 2025

Projects should provide incremental updates of their progress to be published monthly, to help illustrate project journeys. 

Projects should be submitted to be included in the judging: July 31st 2025 

Submitted projects will be reviewed and invites given to DATE 26: [TBC] September 2025

Further judging announcements to determine a place on the target sponsored shuttle: Deadline TBC.

During the conference the best project entries from both tracks will be sponsored to present at DATE 2026.

Rewards/ Prizes: 

Where rewards or prizes are given, they will be for the best project(s) in each track, as determined by the organizers.  Rewards including invites and subsidies for travel to conferences and costs associated with silicon tape out of projects designs.

Judging: 

The judging criteria will centre on how effectively (a) teams achieve self-defined goals and (b) the extent to which the journey has the potential to assist other research groups around the world to push research and development boundaries. The contest theme is open to all manner of research topics, without prescription. 

In terms of the relative balance of judging criteria, the focus is on shared improvement in line with our aims, the distribution will be as follows: 

• Project Progression (40%): Overall management of the project. Commitment to providing regular community updates to SoC Labs that help draw others in (these may include both progress and setbacks/calls for help using various communication channels).  

• Reusability and impact (40%): the potential to assist other research groups around the world to push research and development boundaries. Especially verification efforts where academic activity is less well developed. And that promote broader collaboration with other disciplines, physicists, chemists, mechanical engineers, clinicians, etc.

• Technical complexity (20%):  for the type of track and quality of implementation . 

The judging panel will be geographically balanced and will include judges with specific interest in the three key aspects, community, reusability and technical complexity. 

IP statement:

Teams are encouraged to share their designs where relevant. The default position is that third parties should be able to recreate the outcomes of any projects submitted to the competition.  If there is some aspect of your design that is sensitive, you may submit details of the method rather than the IP block details itself. Any IP statements and conditions of use should be made clear.

More details: 

We will be posting some additional details here and responding to any frequently asked questions. You are welcome to add any questions by using the comment field below.