nanoSoC is the entry level reference design within SoC Labs. It provides a simple M0 microcontroller System on Chip ("SoC") that can be easily extended for design and evaluation of research blocks or subsystems. nanoSoC is adapted from the Arm Cortex-M System Design Kit, CMSDK, which provides verified IP blocks, associated software, verification assets and documentation. nanoSoC has been architected to be a reusable SoC design that can add memory-mapped experimental hardware while simplifying the SoC design process with seamless transition from FPGA prototyping to physical silicon fabrication and evaluation using common verification methods throughout the design process.

It is deal for small academic projects that can be undertaken by PhD or other students to evaluate research hardware such as a custom accelerators or signal processing subsystems with a low cost of fabrication and evaluation. nanoSoC is silicon proven using the TSMC 65nm process.

How does nanoSoC extend the base Arm IP

Modern industrial design practice has progressed beyond a stepwise refinement method to include more agile iterations and prototyping as well as the adoption of reusable design patterns. A key to support such method is always having at any stage a view of the design that can be verified and tested, often via Continuous Integration and Deployment for Verification. Such an approach requires not just starting the design process looking at major functional needs but starting with creating the basis of a deployable design as a starting point. Functional features can be added at any point knowing they can be deployed, verified and if necessary debugged. 

nanoSoC provides this reusable, deployable, verifiable, base reference design. It extends the base arm Cortex-M0 based microcontroller with pad-ring support ready for silicon implementation. This supports ASIC evaluation and debug from early stages of the design process. The address map and bus matrix support expansion memory regions for experimental sub-systems. It provides and FT1248 interface for off chip communication to an external test bench supporting both FPGA and final ASIC hardware verification using common assets. A modified boot monitor and run-time software load process as well as "Tarmac" support for both RTL and gate-level tracing and external debug control allow verification throughout the design process.

By adopting the nanoSoC reference design an academic project can progress easily through the design process in an agile manner knowing that, if at a later stage a redesign of some aspect is necessary, the re-verification of the design is easily actioned. Throughout the design process, block-level designs and verification works in parallel with system and chip-level design and verification.

PGA Flow for initial design stages

An aim of SoC Labs is to simplify transition from FPGA to full ASIC flow. While FPGA environments speed up initial design flow stages an over reliance on components within the Processing System fabric of the FPGA can act as a later barrier to full ASIC flow. The nanoSoC reference design and example FPGA design flow, instantiate a chip level just inside the pad-ring within the FPGA overlay that is independent of Xilinx system IP apart from basic provision of clocking and reset control.  An AXI based "socket“ mimics pad ring connections to ensure the full SoC design is synthesizable, can be verified and is functional for an ASIC tape out.

Extending the nanoSoC reference design

There are a growing number of SoC Labs projects that extend the core nanoSoC reference design. The initial collection of projects using the nanoSoC design were implementing custom accelerators for Machine Learning based inference. Such IP extensions require very efficient transfer of data across the System of Chip bus fabric. The nanoSoC design can be extended by DMA controllers, such as the DMA 230, DMA 350 from Arm or custom controller IP. More recent project have been developing analog parts for subsystems such as sensing. Additional IP such as Analog to Digital Converters ("ADC") and Phase Locked Loops ("PLL") have been used to extend nanoSoC based system capabilities.  

ASIC Flow for back end design stages

The nanoSoC reference design has been certified using a number of Electronic Design Automation suites from the major industry vendors as well as open source alternatives. 

Verification

Students and academics can benefit from shared resources especially verification efforts which are often a weak point in academic projects. nanoSoC is based on the Arm Cortex-M System Design Kit (CMSDK) reference design which provides pre-verified IP and verification assets which can be extended. nanoSoC extends these to provide a continuous and common verification process throughout the design and post fabrication evaluation processes.

Post fabrication design evaluation

The aim for the evaluation environment for nanoSoC based fabricated ASIC die was to provide a low cost test board that also mirrors the design verification environment, simplifying adoption and extension for any project. The board uses two inexpensive RP2040 chips. One provides a  Serial Wire Debug (SWD) and UART debugger interface, used to monitor internal status and debug nanoSoC system. The other configures and interfaces to the nanoSoC system. The RP2040  PIO interfaces allow for custom data transfers, enabling communication via the FT1248 interface of nanoSoC to load code and data from the micro-SD Card or to display results and measurements of system performance via a small LED screen.