Following on from our successful “Bridging the Skills Gap” contest in 2023 we are pleased to announce the “Understanding Our World” SoC design contest for 2024/25.
There are many challenges to address in the world, not least those enshrined in the UN Sustainable Development Goals (SDGs). Society requires innovation in new technologies in order to achieve these goals. Many real-world problems need improved real time understanding of environments of different kinds and our impacts upon them. Sustainable monitoring and management of the external environment demands efficient gathering of data for compute to act on as the first stage of unlocking solutions - from climate change, deforestation, pollution to water use and beyond. The world around us has numerous phenomena, physical and chemical properties that can be sensed including motion, sound, magnetic fields, light, liquids, gases and many more. Innovation is always evolving new forms of sensing our world. Advances are occurring in all aspects of the chain from real world analogue to virtual digital domain processing, in sensing, actuating, conditioning, communication, intelligent processing and overall efficiency of the system.
Gathering various kinds of real-world data has its own challenges in terms of analogue to digital signal conversion and the related design of an efficient SoC. Use cases for how compute can help solve real-world problems are increasingly diverse – a trend which, in turn, makes System on Chip (SoC) design and development skills ever more important.
As with the 2023 contest we will have two alternate tracks:
- Collaboration/Education track focuses on developing SoC design skills within the academic community and broadening the range of institutions undertaking SoC design activity. The focus is not on the hardware design but on how teams develop community collaborations and clearly show institutional and individual skill development in SoC design. It does no require a unique hardware design. Teams can reuse design from other groups either for a new application or simply as a skills development activity; perhaps forming a collaboration to re-purpose open-source IP into community re-usable IP. Groups interested in working with other prospective collaborators should post details of their Arm-based project idea to SoC Labs, including enough detail of progress to date to help others engage. SoC Labs will try and help with the formation of shared community hardware projects. Alternatively, academics involved in teaching SoC design may submit a project summary detailing their approach, including benefit for the community.
- Hardware Implementation track focuses on innovative design for a mixed signal SoC containing both analogue front end and digital components. The design can address one or more of the many areas of interest in mixed signal systems, calibration, accuracy/sensitivity, noise, energy efficiency and many more. The design will highlight the use of data about the external environment within the SoC and processes by which it is efficiently converted from analogue signals to digital forms so that compute can operate on it. The analogue and digital parts have different design characteristics and their efficient integration into a mixed signal SoC design is the focus of this track. The application area is open and could range from a simple novel sensor with a single signal to a more complex pixel-based sensor platform requiring highly parallel signal processing.
This is an online contest with different rewards for the different tracks and activity types. The contest is open to universities or research institutes, subject to the eligibility criteria below.
People taking part in the competition will create a new ‘Competition’ project. A project has a timeframe and uses the two other significant aspects of a SoC development, the selection of technology or IP blocks that make up the SoC and the design flow that is followed from specification through to final instantiation of the system. We have a growing number of example flows using both industry EDA tools and open-source alternatives. To make things easy for people to engage with the contest we have created reference SoC designs, eg. NanoSoC and an example competition design flow to follow - but you can use others. We hope to add additional new training materials in the coming months.
The contest is being supported by the Semiconductor Education Alliance partners. The partners will be assisting the teams and competition in a variety of ways to ensure the community are successful. The best entries will be supported by Arm to attend DATE 2025. Arm and other partners will also help develop opportunities to join appropriate ASIC fabrication shuttles and will contribute towards their cost as part of the competition reward. Teams interested in taping-out their designs should include details of their proposed technology and design flow requirements.
Competition opens: February 2024
Formal project ‘launch’ (including those already in flight): March 25th 2024.
Projects should provide incremental updates of their progress to be published monthly, to help illustrate project journeys.
Projects should be submitted to be included in the judging: July 31st 2024
Submitted projects will be reviewed and invites given to DATE 25: [TBC] September 2024
Further judging announcements to determine a place on the target sponsored shuttle: Deadline TBC.
During the conference the best project entries from both tracks will be sponsored to present at DATE 2025, March 2025.
Only Arm processor-based designs will be considered. The Arm Academic Access (AAA) program is open and ready to receive applications from universities and research institutes to provide access a suite of Arm IP to empower your work on Arm.
The contest is open to research groups with members working within a university/research institution or individual academics involved in SoC Design teaching. Research groups applications can also be from postgraduate students, but applications from postgrads should be supported by a senior member of staff in the same institute who is supervising them. Multiple applications from the same institution can be submitted and supervisors can support more than one postgrad student.
Entry submission and applying:
Entry is via this site. You will need to sign up to SoC Labs as described on the home page. When you are logged in, a Project summary should be submitted via the ‘My Contributions’ tab and dropdown at the top right. You need to use the ‘Add Project’ action. Alternatively: Collaboration/Education tracks can use this link to create an entry; Hardware Implementation tracks can use this link to create an entry.
Submissions take the form of a project summary of no more than 350 words, written in English. For those interested in the Collaboration/Education track you should consider providing a set of milestones that help show how your SoC design skills development project will be demonstrated.
Where rewards or prizes are given, they will be for the best project(s) in each track, as determined by the organizers.
The judging criteria will centre on how effectively (a) teams achieve self-defined goals and (b) the extent to which the journey has the potential to assist other research groups around the world to push research and development boundaries. The contest theme is open to all manner of research topics, without prescription.
In terms of the relative balance of judging criteria, the focus is on shared improvement in line with our aims, the distribution will be as follows:
- Commitment to providing regular community updates to SoC Labs that help draw others in (these may include both progress and setbacks/calls for help using various communication channels) (40%)
- Reusability and impact - the extent to which the journey has the potential to assist other research groups around the world to push research and development boundaries (40%)
- Technical complexity for the type of track and quality of implementation (20%).
The judging panel will be geographically balanced and will include judges with specific interest in the three key aspects, community, reusability and technical complexity.
Teams are encouraged to share their designs where relevant. The default position is that third parties should be able to recreate the outcomes of any projects submitted to the competition. If there is some aspect of your design that is sensitive, you may submit details of the method rather than the IP block details itself. Any IP statements and conditions of use should be made clear.
We will be posting some additional details here and responding to any frequently asked questions. You are welcome to add any questions by using the comment field below.