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Optimized Local ML Models on nanoSoC Cortex-M0 Platform

Overview

Custom ML Model Accelerator on NanoSoC Cortex-M0

Project is based on NanoSoc reusable MCU platform where the custom machine-learning (ML) inference accelerator to the Cortex-M0 SoC.

Tenserflow is used for custom ML model training (TFLM), using TensorFlow Lite for Microcontrollers port model will be ported to C++ and compiled for Arm Cortex-M0 platform that is suitable to run on NanoSoC. After successful software port, trained neural-network model is converted into hardware accelerator using high-level synthesis (HLS) hls4ml for inference in FPGA and connected via an accelerator wrapper on the AHB-Lite bus. Accelerator is controlled by the software running on Cortex-M0.

This platform will be validated on FPGA first and then prepared for tapeout.

This project is meant to become a reusable platform for PhD and student projects in local custom embedded ML models.

Approach

The most ideal scenario is to run works in parallel so that each approach can be compared with the software-only implementation as a baseline.

Software-OnlyRun models with TFLM on bare NanoSoC Cortex-M0. Benchmark the metrics of running models to get the baseline parameters for comparing custom hardware solutions.
Custom Hardware AcceleratorGenerate RTL for the model with hls4ml and integrate to the NanoSoC platform. Write custom drivers and compare performance with the software-only baseline.
Dedicated NPUExplore the possibility of an Arm Ethos-U based platforms on SoC Labs for heavier workloads such as real-time human recognition.

 

 

 

Project Milestones

Getting StartedProject StructureContinuous Integration and Deployment for verification
Architectural DesignSpecifying a SoCdata modelIP SelectionVerification Methodology
Behavioural DesignBehavioural ModellingGenerate RTLRTL VerificationSimulation
Logical DesignTechnology SelectionSynthesisDesign for TestLogical verification
Physical DesignFloor PlanningPreparationClock Tree SynthesisRoutingTiming closurePhysical VerificationTape Out
Post Silicon
Complete
In Progress
Not Started
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  1. Project Structure

    Design Flow

    Project Structure

    Project Structure

    Target Date
    Completed Date
    Result of Work

    Taking submodule approach and all files and other repositories used by the project is inside forked NanoSoC.

  3. Specifying a SoC

    Design Flow

    Specifying a SoC

    Specifying a SoC

    Target Date
    • Official project page.
    • Architectual UML diagrams.
    • Accelerator specificatoion

  4. data model

    Design Flow

    data model

    data model

    Target Date
    • Trained TFLite model on real data to detect voltage discharges.

  6. Getting Started

    Design Flow

    Getting Started

    Getting Started

    Completed Date
    • NanoSoC running on PYNQ-Z2.
    • TFLM toolchain setup.
    • Custom TF model built and running on FPGA.
    Result of Work

    NanoSoC with no accelerator runs on PYNQ.

    TFLM toolchain set up and build on Cortex-M0 platform.

    MNIST model runs on FPGA.

  8. Generate RTL

    Design Flow

    Generate RTL

    Generate RTL

    Generate custom ML model using hls4ml to HLS and then to RTL.

  9. RTL Verification

    Design Flow

    RTL Verification

    RTL Verification

    • Run on FPGA with custom accelerator.
    • UVM tests for protocol implementation.

Comments

Hi,

Thanks for sharing the project details. We have some experience now of this type of flow. I would suggest a quick look at this project. 

Arrhythmia Analysis Accelerator : A-Cube

Sadly for me there is a lot more detail and knowledge associated with this project that we can share but has not been captured in the project over time. I tried to capture some points in the comments. We are keep to collaborate and there is much we can share with you.

John.

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Project Creator
Profile picture Manfredas

Student, Researcher at Kaunas University of Technology
Research area: Digital design, digital design verification
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Technology

Cortex-M0 Cortex-M0

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