Interference Detection and Mitigation Accelerator for Automotive Radar SoCs
Advancements in electronics, wireless communications, and sensing technologies have made possible a multitude of smart sensing features in automotives. Integrating high-frequency sensors, digital signal processors and hardware accelerator engines on a single system on a chip (SoC) enhances sensing computation potential of radar sensors utilized in automotives. However, as the number of vehicles equipped with such wireless SoC sensors increases so does the likelihood of mutual wireless interference among these sensors leading to performance degradation and compromising safety of such systems.
The main aim of the project is to design advanced digital signal processing modules for wireless radar sensor SoCs which can detect and mitigate mutual interference. High level system model of the proposed project showing various modules is presented in the above figure. Our interference-awareness and mitigation design will allow the use of interference mitigation module on an as-needed basis in the SoC. This means that interference mitigation processing chain will only be enabled when required which has the potential to enable power savings in the SoC.
Project Milestones
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Milestone #1Target Date
Architectural Design of Accelerator Modules
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Modelling/Simulation
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Accelerator Design Implementation
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Milestone 4: RTL generation using Xilinx Tool
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Milestone #5Target Date
Verification using Xilinx Tool
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Milestone #6Target Date
FPGA flows
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Milestone #7Target Date
NanoSoC reference design exploration
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Milestone #8Target Date
Developing ASIC (65 nm) flow and integration possibility of accelerator with nanosoc
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Milestone #9Target Date
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Milestone #12Target Date
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Milestone #13Target Date
Team
Comments
Analog Front end
Thank you for showing interest. Our proposed SoC system processes complex baseband mmWave radar IQ samples.
Our design works in purely digital domain on FPGA-SoC (PL with ARM PS). Our interest is of course to be able to integrate
our logic part of the design (accelerator) via some wrapper to your SoC flow.
Please note that constructing mmWave analog front end is serious amount of extra and non-novel work which does not suits the University research needs.
For testing the system we use real Radar IQ data captured using TI radar chip and communicated via ethernet or USB or some other port.
I hope this clarifies and answers your question.
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Analog front-end
Hi Zaheer,
This looks like a very interesting project. I wonder if you might be able to add a bit more detail on what the front end of this looks like?
I'm just wondering what kind of signals you are recieving, are these modulated (and in need of demodulation) or is the aim to have high speed ADC's that can work in GHz range?