Competition 2024
Competition: Hardware Implementation

Battery Management System-on-chip (BMSoC) for large scale battery energy storage

Battery storage systems are an important source for powering emerging clean energy applications. The Battery Management System (BMS) is a critical component of modern battery storage, essential for efficient system monitoring, reducing run-time failures, prolonging charge-discharge lifecycle, and preventing battery stress or catastrophic situations. The BMS performs functionalities such as data acquisition and monitoring, battery state estimation, cell equalization, and charge protection, making it computationally intensive to manage large scale battery storage. This necessitates the development of a System-on-chip (SoC) solution which can perform real-time and high speed battery management with improved accuracy and efficiency.
The proposal envisages the development of energy-efficient and lightweight mixed signal Battery Management SoC architecture. The proposed SoC architecture comprises an Analogue front-end (AFE) for voltage, current, and temperature sensing, Analogue to digital converters, a charge protection circuit (overvoltage, undervoltage and overcurrent conditions), a digital signal processing unit, and a master controller with required communication interfaces as shown in the Fig. The AFE architecture also incorporates charge equalization using active cell balancing. Active balancing redistributes charge among cells with imbalanced characteristics as opposed to dissipating energy in the form of heat (as in the case of passive balancing solutions), leading to improved thermal management. The mixed signal SoC offers improved hardware and software components optimization, leading to higher system performance with low latency for data handling and processing.
The SoC architecture can handle multiple cells by integrating low speed sensors with a high speed processor, enhancing the computational capability of edge devices. Additionally, the SoC offers access to cloud resources through the radio transceiver and multiple SoCs can be integrated to form a BMS cluster to provide cloud-based management capabilities. The scalable architecture also promotes ease of integration and reduces the development time for different battery configurations which varies across applications. With modern battery technology evolving rapidly, the SoC provides reconfigurability for adapting to newer technologies without the need to change the underlying processing hardware. The resulting scalable and flexible BMSoC makes it applicable across applications from IoT devices to automotive and renewable energy grid storage.

Project Milestones

  1. Architectural Design

    Target Date
    1. Layout Planning
    2. Partitioning of Analog and Digital Regions
  2. Logical Design

    Design Flow
    Target Date

    Domain Specific Design

    1. Analog Domain

      a. Schematic Design

      b. Simulation

       

    2. Digital Domain

      a. Behavioural Simulation

  3. Physical Design

    Design Flow
    Target Date
    1. Analog Design
      a. Physical layout and verification
      b. Post layout simulation
    2. Digital Design
      a. Synthesis
      c. Floor Planning
      b. Place and route
      c. Functional verification
  4. Physical Verification

    Target Date
    1. Full chip assembly & physical verification
    2. Mixed-signal functional verification
  5. Milestone #7

    Target Date
  6. Target Date
  7. Milestone #8

    Target Date
  8. Milestone #9

    Target Date
  9. Milestone #10

    Target Date
  10. Milestone #11

    Target Date
  11. Milestone #12

    Target Date
  12. Milestone #13

    Target Date

Team

Research Area
VLSI systems resource-constrained applications, Low Power Design Techniques, Machine learning hardware design, Signal Processing Algorithm and VLSI Architectures, Digital Arithmetic, Biomedical Devices. AI/ML, Nanoscience & Technology
Role
Professor

Comments

Hi,

Thanks for joining. We look forward to collaborating and seeing the project develop. Have you though about the initial Architectural Design milestone? Perhaps you can add an initial idea of how long you feel that will take. It might help to get the project off on the right track. If you have any questions please ask.

John.

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Project Creator
Rashi Dutt

Researcher at Indian Institute of Technology Hyderabad (IITH)
Research area: Low power VLSI architecture
ORCID Profile

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