Known Good Die
Tutu Ajayi / University of Michigan

65nm SoC with M0 for mixed signal design inc. temperature sensors

The SoC uses a M0 core with 2 PLLs, 3 LDOs, 16KB SRAM, and 2 temperature sensors and was fabricated to aid in the evaluation of a mixed-signal SoC design framework with a number of analog block generators. It uses the AMBA™ APB protocol as the register interface to all blocks.

The temperature sensor has an area of 2,620µm2 . A 2-pt calibration is performed at 0°C and 80°C. Measured results show a sensing range between -20°C and 100°C with an accuracy of ±4°C. The generated SRAM has an area of 0.68mm2 and a custom bitcell area of 0.4mm2 .

The FASoC design framework supports mixed-signal SoC development using a cell-based design methodology to combine analog components with digital circuits on the same chip. The framework takes user design constraints and uses a suite of automated generators for analog blocks. It is process agnostic and the physical design of all blocks, including analog, is achieved using optimized synthesis and automatic place-and-route (APR) flows in commercially available tools.


Community lead at University of Southampton


Cortex-M0 Cortex-M0