The SoC uses a M0 core with 2 PLLs, 3 LDOs, 16KB SRAM, and 2 temperature sensors and was fabricated to aid in the evaluation of a mixed-signal SoC design framework with a number of analog block generators. It uses the AMBA™ APB protocol as the register interface to all blocks.

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A 3D integrated sensor system with an M3 microprocessor powered by solar cells with battery storage. It operates near threshold at 73kHz with the Wake-Up Interrupt Controller only bringing the core out of ultra-low leakage mode to take the necessary sensor readings. The system uses powe…