megasoc re-usable SoC platform

Rationale

megasoc has been designed to provide a complex SoC component that can 'host' and support the development and evaluation of research components or subsystems. The design allows for seamless transition from FPGA to physical silicon implementation via a pre-verified programmable control system that allows reuse of software and diagnostic functionality to facilitate the configuration, control and diagnostic analysis of research hardware such as custom accelerators or signal processing.

The design is based on an Arm Cortex-A53 CPU core with inspiration from the Corestone 1000 subsystem from Arm. megasoc allows the reuse of the AAA pre-verified IP, documentation and software but it is architected to support simple 'bolting-on' of experimental hardware. The aim of megasoc is to provide a fully Linux capable SoC whilst minimising the cost of physical silicon production.

Technical Overview

megasoc is a complex SoC utilising the Cortex-A53 processor with pad-level support for silicon implementaation. Included is:

CPU - Armv8-a Cortex A53 processor
Interrupt Controller - GIC 400
Software Debugger - Arm DAP-lite
Boot ROM
XiP QSPI - For program or BIOS
SRAM
NIC 400 System Bud
DRAM controller
DMA for system support - Off-chip mem to DRAM
Peripherals (UART, Timers, etc)

Architecture

The overall architecture is as shown below. This has been seperated into 2 main sections, the CPU and System sections. Development so far has been focused on the CPU subsystem, as we are currently exploring options for sourcing the IP for the ethernet, USB, DDR and PCIe controllers.

Address Map

The Cortex A53 has a 40-bit address interface, this gives a total addressable space of 1 TB. For now a simplified 32 bit address map is being created, it is likely that any higher address will be used to expand the DRAM and possibly for direct access from the CPU to the communication interfaces (PCIe, USB, Ethernet) if possible, although these will all likely be controlled by DMA transfers.

Currently this address map is unoptimised (some regions are much larger than neccessary, and there are a few empty regions which will likely be filled as development progresses.

MegaSoC CPU Address Map
Start Address	End Address	Region	Size
0x00000000	0x0000FFFF	Boot Rom	64 KiB
0x00400000	0x007FFFFF	QSPI Flash	4 MB
0x00800000	0x0080FFFF	SRAM	64 KiB
0x01000000	0x0100FFFF	Flash and Cache Control	64 KiB
0x01010000	0x01011FFF	DMA Control	8 KiB
0x01100000	0x01107FFF	GIT 400 Control	32 KiB
0x40000000	0x5FFFFFFF	Peripheral	512 KiB
0x60000000	0x7FFFFFFF	Debug	512 KiB
0x80000000	0xFFFFFFFF	DRAM	2 GB

CPU Interrupts

The GIC-400 generic interrupt controller supports a maximum of

MegaSoC Cortex A53 Interrupt Map
IRQ Number	Source
32	DMA350 Channel 0 interrupt
33	DMA350 Channel 1 interrupt
34	DMA350 Channel 2 interrupt
35	DMA350 Channel 3 interrupt
36	DMA350 common interrupt
37	UART0 Transmit interrupt
38	UART0 Recieve interrupt
39	UART0 TX Overrun interrupt
40	UART0 RX Overrun interrupt
41	UART0 Combined interrupt
42	TIMER0 interrupt

Communication channel

Currently implemented is a single UART channel for off-chip communications.

Pinlist

Pin/Port	Function
REF_CLK_XTAL1/2	Main System clock from crystal oscillator
RT_CLK_XTAL1/2	Real time clock input from crystal oscillator
PORESTn	Active low power-on-reset
nSRST	Active low System reset
GPIO_P0[15:0]	GPIO Port 0
GPIO_P1[15:0]	GPIO Port 1
QSPI_SCLK	Clock output from QSPI controller
QSPI_nCS	Chip select output from QSPI controller
QSPI_IO	Data I/O from QSPI controller
FT_CLK	FT1248 Clock
FT_SSN	FT1248 Chip Select
FT_MISO	FT1248 input
FT_MIOSIO	FT1248 IO

Using megaSoC

If you'd like to use megasoc for your custom hardware, you can fork or clone the megasoc project git repository. This SoC reference design is still under development, expand the V1 Tapeout section below for more details.

megaSoC V1 Tapeout

Work is currently underway to tapeout megaSoC in 2026. This initial version will be a "Minimal Viable Product" version of megaSoC. This version will not have the complexity of high speed external interfaces and the PCIe, USB and Ethernet subsystems.

The aim for the initial tapeout of megaSoC is to prove the core compute system, the fabrication flows and provide a good baseline of information to the community on taping out an A-class processor on an advanced technology node. As with the first version of nanoSoC some application scenarios may be limited it will serve as a good foundation for future improvements.

These two controllers will be replaced with an SDIO controller (ZipCPU SDIO) and a UART controller (PL011 from ARM)

Network over UART

Whilst not idea, networking is possible over UART. And this is the plan for the MVP implementation of this megaSoC-lite version. Network communication is possible using packages like PPP in linux (an example on how to set this up between 2 raspberry pi's). The PL011 from Arm has been chosen as it allows for hardware flow control which is ideal for this application.

SD card filesystem

Ideally a very high speed non-volatile memory would be used for the filesystem using a PCIe interface to integrate an M.2 SSD device. However, it is quite common practice to use SD cards for such applications. The implementation of a PCIe interface and associated PHY for the SD controller is the target for a later version. The ZipCPU project is mostly focused around FPGA implementations and so whilst there is a lot of information available it would require a custom PHY implementation. Without a PHY the system would be limited in the bandwidth achievable for the SD card.