megaSoC is a high end reference design within SoC Labs. It provides a high performance System on Chip (SoC) using the Arm Cortex A53, that can be extended for design and evaluation of research blocks or subsystems. megaSoC is loosely based on the Arm Corstone 1000 subsystem, but with a simplified architecture to reduce tape out costs (no big.Little architecture, no security features, single processor/cluster design). megaSoC has been designed to be a reusable SoC design that can add memory-mapped experimental hardware, while simplifying the SoC design process with seamless transition from FPGA prototyping to physical silicon fabrication and evaluation. 

To reduce the costs associated with academic routes to tape out, megaSoC is designed as a chiplet based subsystem. The main SoC will be an independent chiplet with research project accelerator subsystems on separate chiplets. This means that the central megaSoC chiplet can be taped out once, giving 100 separate dies that can be used on 100 separate projects. This makes the complex A class SoC systems a one time upfront cost, the ongoing cost of multiple projects will be greatly reduced. It will improve efficient use of silicon, as the same processor etc. will not require fabrication every time you make a new custom hardware SoC. 

megaSoC is ideal for an academic team to evaluate research hardware in a SoC that can provide significant CPU performance, such as high speed pre/post processing data, and/or complex software stacks such as a Linux operating system. megaSoC is still under development and we welcome collaboration.