I2C/I3C

Inter-Integrated Circuit (I²C or IIC) 

This standard is one of the most common synchronous serial communications protocols for chip-to-chip communications. It’s most often used for board based communication between microcontrollers/processors and off-chip memory, sensors, and display driver devices. I2C can be an attractive choice for communication when the need for a low pin count is more important than the need for high bandwidth. The I2C standard defines several speed grades: standard mode – 100 kbps, full speed – 400 kbps, fast mode – 1 Mbps, and high seed 3.2 Mbps. 

The main advantage of I2C is that it can be used for multiple-manager, multiple-subordinate communications with the a very low pin count of only 2 pins. These two pins are a clock and data pin. 

The I2C protocol enables transfer to be broken up into frames, with an address frame 7-10 bits, then one or more data frames. Between each frame is an acknowledge bit that allows for the receiving device to let the transmitting device know that a transfer was successful. In I2C the data is read each clock cycle. 

I3C (Improved Inter-Integrated Circuit) 

This standard was developed to address some of the limitations with I2C. Mainly these are, the static addressing and low data rates. I3C can dynamically assign addresses to subordinate devices, which can be important particularly in applications where a large number of subordinate devices are used. For example if implementations are the same type of chip, as manufacturers normally only set aside a few bits of the address as configurable in I2C devices. 

 The I3C standard allows for double-data rate transfers where data is sampled on the rising and falling edge of a clock. With the DDR signaling, a bandwidth of approximately 25 Mbps is achievable. The downside of this protocol is it requires more complicated hardware to implement, so more area on chip and more project time/effort in development and verification.