Member for1 week Name Karthik Ja SoC Labs Roles Registered User Projects Articles Interests Design Flow RTL Verification Universal Verification Methodology Logical verification Technology BP140 AXI Memory Interface XHB-400: AXI4 to AHB-Lite Bridge Authored Comments User statistics My contributions : 0 My comments : 0 Add new comment To post a comment on this article, please log in to your account. New users can create an account.
Add new comment
To post a comment on this article, please log in to your account. New users can create an account.