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Member for
4 months
Name
Karthik Ja
SoC Labs Roles
Registered User
Independent

Projects

Articles

Interests

Design Flow

RTL Verification

RTL Verification

Universal Verification Methodology

Universal Verification Methodology

Logical verification

Logical verification

FPGA SoC Prototyping design flows

FPGA SoC Prototyping design flows

Technology

BP140 AXI Memory Interface

BP140 AXI Memory Interface

XHB-400: AXI4 to AHB-Lite Bridge

XHB-400: AXI4 to AHB-Lite Bridge

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