Member for
11 hours 15 minutes
Name
Justin Das
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10
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Title Updated date Comment count
High Capacity Memory Subsystem Development 59 minutes 1 second ago 32

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Subject Comment Link to Comment
Newly Joined to the Project - Justin Das

 

Name: Justin Das

Area of Interest: RTL Design(Verilog, System Verilog), IP and SoC Design.
Please help me with the steps to ramp up this project.

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My contributions
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1
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1
Overall contributor
:
#76
2024 contributor
:
#4
December 2024 contributor
:
#4

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