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Title	Updated date	Comment count
High Capacity Memory Subsystem Development	2 weeks 4 days ago	36

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Hi Srimanth,I am interested…	Hi Srimanth, I am interested in working on this project, I'm new to the industry not sure how much I'll be able to help, but I'm driven and passionate about doing such hands-on projects. Skills : I mostly work with netlist CDC and formal Datapath validation, good with python, TCL scripting, c, c++ , verilog, handy with linux. I have also worked on an accelerated hardware project, for our btech final year project we developed a HEVC decoder using xilinx HLS, deployed it on zedboard soc FPGA, loaded linux and developed the driver to interface with the accelerator glued together by AXI4 interface. Looking forward to hearing from you !	view

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Timing Data / PHY and data path

There are two areas that are need driving forwards currently, the timing data and the PHY and data path. You will see in the slack I have been trying to move forward the discussion on the design of the system to instantiate the timing data and also the system under test in general.

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