Member for

1 day 1 hour

Name

Geethika Bandara Jayasekara

Role

Student

SoC Labs Roles

Registered User

Projects

Title	Updated date	Comment count
High Bandwidth Expansion Subsystem	1 day ago	0

Articles

Interests

Getting Started with SoC Labs

Hardware design

Firmware

RF and Analog Design

Design Flow

Behavioural Design

FPGA SoC Prototyping design flows

Getting Started

Logical verification

Technology

On-Chip Communication

Advanced Microcontroller Bus Architecture

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Authored Comments

User statistics

My contributions

:

3

My comments

:

0

Overall contributor

:

#49

2026 contributor

:

#1

February 2026 contributor

:

#1

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