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Udara Ranabahu Suraweera Arachchi Suraweera Arachchige
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FPGA SoC Prototyping design flows

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Almost.. 😀

Hi John, Thanks for your comment.

Yes! I have designed an IP on CNN parallel acceleration and first verified it on FPGA. To learn GDS synthesising using SKY130A PDK and open-source tools, I have used that CNN IP with OpenLane RTL2GDSII flow and generated a physical design layout with all preliminary checks cleared. 

However, as of today, the project is still far away from sign-off for tapeout, as the design needs to be tested extensively for its characteristics. There is a steep learning curve for using open-source tools for design characterization, and I am actively working on it. 

Regards!

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Hi,

Did I see that you designed  a custom-built Convolutional Neural Network (CNN) Accelerator Engine IP as a part of your postgraduate studies and you taped it out on 130-nm process node using the Skywater Technology SKY130A PDK and open-source tools?

Hi John, Thanks for your comment.

Yes! I have designed an IP on CNN parallel acceleration and first verified it on FPGA. To learn GDS synthesising using SKY130A PDK and open-source tools, I have used that CNN IP with OpenLane RTL2GDSII flow and generated a physical design layout with all preliminary checks cleared. 

However, as of today, the project is still far away from sign-off for tapeout, as the design needs to be tested extensively for its characteristics. There is a steep learning curve for using open-source tools for design characterization, and I am actively working on it. 

Regards!

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