Dear John,

Thanks for your question. In this work, the 32-bit AHB-Lite bus infrastructure are chosen. This choice was based on it is inherently compatible with the open-source ARM Cortex-M3 processor implementation we employ. Within our system, the MCU facilitates the transfer of input/output data between the system memory and the accelerator. The choice of the AHB-Lite bus infrastructure aligns with our design specification. This is because the latency of the trajectory optimization algorithm primarily depends on the computing resources rather than the system bandwidth.

However, we acknowledge that changing to a faster bus infrastrucutre with the integration of a DMA engine is able to reduce the workload of the MCU. This would allow the MCU to handle the additional tasks concurrently.